Datasheet for AM2812

M

Mark (UK)

Guest
Hiya!

I'm looking for the datasheet for the AM2812 FIFO ram. I've tried the
usual suspects with no luck.

Anyone got one?

Thanks. Yours, Mark.
 
In article <buoe3l$efs$1@hercules.btinternet.com>, Mark (UK) wrote:
Hiya!

I'm looking for the datasheet for the AM2812 FIFO ram. I've tried the
usual suspects with no luck.

Anyone got one?
Thanks. Yours, Mark.
Click to expand...
Not a full datasheet, but I do have a 1-page summary sheet.

32 x 8 FIFO. Independent read and write controls.
Data on Di written by a pulse on PL, data ripples down until it
reaches the output or hits another data word.
Data is read by applying a shift out on PD. This dumps the word on Qi
and the next word in the buffer moves to the output.

An output ready signal OR indicates that data is available, and also
provides an empty signal. An input ready (IR) indicates that the
device is ready to accept data and also provides a full signals.
FLAG goes high when the memory contains more than 15 words.

The Am2812 can perform input and output data transfers on a
bit-serial basis as well as on 8-bit words. The input buffer is in
reality an 8-bit shift register which can be loaded in parallel by
PL or can be loaded serially via D0 using the SL clock. When 8 bits
have been shifted in serially, the word automatically moves in
parallel through the memory. The output includes a parallel-to-serial
converter, so data can be shifted out of Q7 by using the SD clock.
After 8 clock pulses, a new 8-bit word appears at the output.

Suffix "A" for 1MHz version, without suffix it's 500kHz. [!]

Pinout: D1 D2 D3 -IR VSS D4 D5 D6 D7 FLAG PL SL VDD Q7
28 27 26 25 24 23 22 21 20 19 18 17 16 15

1 2 3 4 5 6 7 8 9 10 11 12 13 14
D0 VGG OR -MR PD SD Q0 Q1 Q2 Q3 OE Q4 Q5 Q6

That's all it says, I'm afraid.
I guess MR is a reset. No data on what VGG or VDD should be.

Regards,
Mike.
 
Hiya!

Thanks for that info. Infact AMD themselves have been really helpful and
faxed a datasheet (7 pages) to my work fax, which I should be able to
pick up on monday.

I should then be able to scan it and put it on my website - as well as
seeing what these 3 tubes of curious chips I've come across actualy do!!

Yours, Mark.

Remove _ for valid address wrote:

In article <buoe3l$efs$1@hercules.btinternet.com>, Mark (UK) wrote:

Hiya!

I'm looking for the datasheet for the AM2812 FIFO ram. I've tried the
usual suspects with no luck.

Anyone got one?
Thanks. Yours, Mark.


Not a full datasheet, but I do have a 1-page summary sheet.

32 x 8 FIFO. Independent read and write controls.
Data on Di written by a pulse on PL, data ripples down until it
reaches the output or hits another data word.
Data is read by applying a shift out on PD. This dumps the word on Qi
and the next word in the buffer moves to the output.

An output ready signal OR indicates that data is available, and also
provides an empty signal. An input ready (IR) indicates that the
device is ready to accept data and also provides a full signals.
FLAG goes high when the memory contains more than 15 words.

The Am2812 can perform input and output data transfers on a
bit-serial basis as well as on 8-bit words. The input buffer is in
reality an 8-bit shift register which can be loaded in parallel by
PL or can be loaded serially via D0 using the SL clock. When 8 bits
have been shifted in serially, the word automatically moves in
parallel through the memory. The output includes a parallel-to-serial
converter, so data can be shifted out of Q7 by using the SD clock.
After 8 clock pulses, a new 8-bit word appears at the output.

Suffix "A" for 1MHz version, without suffix it's 500kHz. [!]

Pinout: D1 D2 D3 -IR VSS D4 D5 D6 D7 FLAG PL SL VDD Q7
28 27 26 25 24 23 22 21 20 19 18 17 16 15

1 2 3 4 5 6 7 8 9 10 11 12 13 14
D0 VGG OR -MR PD SD Q0 Q1 Q2 Q3 OE Q4 Q5 Q6

That's all it says, I'm afraid.
I guess MR is a reset. No data on what VGG or VDD should be.

Regards,
Mike.
Click to expand...
 
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