datapath of a simple cpu

[Aliki]

Hello all!

I am trying to complete the development of a simple four-instruction CPU
in VHDL. I have developed the control unit, I have written a
four-intruction program in a memory but the top design doesn't work
properly (as it is supposed to). I think that my problem lies in the
register section of the CPU because whenever I make changes in the VHDL of
the register section the behavior of my top model changes.
The source code of the register section follows. Could anyone tell me if
there is anything wrong with the code as it is written? Thank you!
************************************************************
************************************************************
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity data_path_new is
port(
clk: in std_logic; -- this should be clock from the external clock
input, not passed through control unit
reset: in std_logic; -- from external world.
addressout: out std_logic_vector(5 downto 0); -- address lines to
external memory
--ac_hold_out: out std_logic_vector(7 downto 0); -- this signal
allows minitoring the accummulator content
datain: in std_logic_vector(7 downto 0); -- data from external
memory
irbus: out std_logic_vector(1 downto 0); -- instruction register
output to control unit
arload_in: in std_logic; -- address register \
pcinc_in,pcload_in,pcbus_in: in std_logic; -- program counter \
drload_in,drbus_in: in std_logic; -- data register \ FROM
acload_in,acinc_in: in std_logic; -- accumulator \ CONTROL
irload_in: in std_logic; -- instruction register / UNIT
alusel_in: in std_logic; -- alu /
membus_in: in std_logic; -- load memory /
memread_in: in std_logic
);

end data_path_new;

architecture combined of data_path_new is

--*****************************************************
-- internal buses and signals
--*****************************************************
signal intdbus: std_logic_vector(7 downto 0);
signal pc_hold: std_logic_vector(5 downto 0);
signal dr_hold: std_logic_vector(7 downto 0);
signal ir_hold: std_logic_vector(1 downto 0);
signal ac_hold: std_logic_vector(7 downto 0);
signal alu_out_drive: std_logic_vector(7 downto 0);
signal data: std_logic_vector(7 downto 0);
signal mem_data_out: std_logic_vector(7 downto 0);
signal mem_data_in: std_logic_vector(7 downto 0);
signal mem_address: std_logic_vector(5 downto 0);
signal ar_hold: std_logic_vector(5 downto 0);


--*************************************************************
-- ALU
--*************************************************************

component alu
port(
alu_in_0 : in std_logic_vector(7 downto 0);
alu_in_1 : in std_logic_vector(7 downto 0);
alu_control : in std_logic;
alu_out : out std_logic_vector(7 downto 0)
);
end component;

begin

-----------------------------------------------------
--****************PROGRAM COUNTER****************--
-----------------------------------------------------
PC: process(clk)
variable mpc:std_logic_vector(5 downto 0);
begin
if(clk'event and clk='1') then
if reset = '1' then
mpc:= "000000"; -- initial value

elsif pcload_in= '1' then -- and membus_in ='0' and pcbus_in ='0' then
mpc:= intdbus(5 downto 0);

elsif pcinc_in = '1' then --and drbus_in ='0' and membus_in= '0' then
mpc:= mpc + 1;

else
mpc:=mpc;
end if;
end if;
pc_hold <= mpc; -- The pc_hold signal holds the current value of the pc
reg in order to pass it to the internal bus


end process PC;



-----------------------------------------------------
--****************ADDRESS REGISTER****************--
-----------------------------------------------------


AR: process(clk)
variable mar: std_logic_vector(5 downto 0);
begin


if (clk'event and clk='1') THEN
if reset = '1' then
mar := "000000" ;
elsif arload_in = '1' then --and membus_in = '0' and pcbus_in = '0'
then
mar:= intdbus(5 downto 0);
else mar:=mar;
end if;
end if;
ar_hold <= mar; -- to memory
addressout <= ar_hold;
-- addressout<=mar;
end process AR;



-----------------------------------------------------
--****************DATA REGISTER****************--
-----------------------------------------------------
DR: process(clk)
variable mdr: std_logic_vector(7 downto 0);
begin
if(clk'event and clk='1') then
if reset = '1' then
mdr:="00000000";

elsif drload_in='1'then --and pcbus_in = '0' and drbus_in = '0' then
mdr:=intdbus;
else
mdr:=mdr;
end if;
end if;
dr_hold <=mdr; --to data bus

end process DR;



-----------------------------------------------------
--****************INSTRUCTION REGISTER****************--
-----------------------------------------------------
IR: process(clk)
variable mir: std_logic_vector(1 downto 0);
begin
if(clk'event and clk='1') then
if reset = '1' then
mir := "00" ;

elsif irload_in = '1' then --and membus_in = '0' and pcbus_in = '0' then


mir:= intdbus(7 downto 6);

else
mir:=mir;
end if;
end if;

irbus<= mir;



end process IR;




-----------------------------------------------------
--****************ACCUMULATOR****************--
-----------------------------------------------------
AC: process(clk)
variable mac: std_logic_vector(7 downto 0);
begin
if(clk'event and clk='1') then
if reset = '1' then
mac := "00000000" ;
elsif acload_in= '1' then --and membus_in = '0' and pcbus_in = '0'
then
--elsif acload_in= '1' then

mac:= alu_out_drive;

elsif acinc_in='1' then
mac:= mac + 1;
else mac:= mac;

end if;
end if;
ac_hold <= mac;
--ac_hold_out <= mac;
end process AC;






--********************************************
-- ALU INSTATIATION
--********************************************
i_alu:component alu
port map(
alu_in_0 => intdbus,
alu_in_1 => ac_hold,
alu_control => alusel_in,
alu_out =>alu_out_drive
);


--*****************************************************************
-- implementation of data bus
--*****************************************************************
intdbus <= pc_hold when pcbus_in = '1' else
dr_hold when drbus_in = '1' else
datain when membus_in = '1';







end combined;

 

[Mike Treseler]

"Aliki" <aliki@> wrote in message news:<db7d8c3eced508a18f615b2b6f2ed67b@localhost.talkaboutprogramming.com>...

I am trying to complete the development of a simple four-instruction CPU
in VHDL. I have developed the control unit, I have written a
four-intruction program in a memory but the top design doesn't work
properly (as it is supposed to).

I assume that you know this from running a simulation
that fetches and executes an instruction.

Look at the first few uS of sim waveforms for us and
tell us what is the first thing that goes wrong after reset.

-- Mike Treseler

 

[Aliki]

Well Mike, the first instruction is an add4 which means that the content of
memory position 4 must be fetched and added to the accumulator. What I see
in the simulator is that the cpu downloads the memory content (27H) but
after that everything goes wrong, the contents in the registers change in
a random sequence (wrong sequence, definitelly different than what is
expected) and the IR(Instruction register) doesn't take any value at all.
The AR(address reg) has the expected values but in a wrong sequence
because after the value of memory position 4 (27H) is downloaded, all the
other contents of the memory are downloaded but the cpu does nothing since
the IR Reg. (which drives the control unit) has no value.

Thank you, Aliki.

 

[Mike Treseler]

--*****************************************************************
-- implementation of data bus
--*****************************************************************
intdbus <= pc_hold when pcbus_in = '1' else

intdbus <= "00" & pc_hold when pcbus_in = '1' else

-- Mike Treseler