data_in data_out

[krby_xtrm]

how can this code snippet be a synthesizable material

....
generic ( size : integer := 32 -- or any from 4,8,16,32, & 64
size2 : integer := 8) -- for data_out
port ( data_in ((size - 1) downto 0);
data_out((size-1) downto 0))
)

....
variable cnt : integer range 0 to 3:=0; -- to cut data into 4
....

data_out <= data_in((size-1)+cnt downto (size-1)*cnt)
cnt := cnt + 1; -- increment

*what i want in this code is that everytime the clock arrives data_out
gets a part of the divided by 4 data_in

like 1st clock part_1_of_4 ... last clk part_4_of_4


with this, we can illiminate typing of the downto's from 0 to 64 or any
range, w/c is a very hard task...

.... or is ther another way to do this?


-krby_xtrm

 

[Rolf Eike Beer]

Von krby_xtrm:

how can this code snippet be a synthesizable material

...
generic ( size : integer := 32 -- or any from 4,8,16,32, & 64
size2 : integer := 8) -- for data_out
port ( data_in ((size - 1) downto 0);
data_out((size-1) downto 0))
)

...
variable cnt : integer range 0 to 3:=0; -- to cut data into 4
...

data_out <= data_in((size-1)+cnt downto (size-1)*cnt)
cnt := cnt + 1; -- increment

*what i want in this code is that everytime the clock arrives data_out
gets a part of the divided by 4 data_in

Untested and will not work for size=4 and size2=8

process(res_n, clk)
subtype cnt_t is natural range 0 to size/size2 - 1
variable cnt: cnt_t;
begin
if (res_n = '0') then
cnt := 0;
elsif rising_edge(clk) then
data_out <= data_in((cnt + 1)*size2 - 1 downto cnt*size2);
if (cnt = 0) then
cnt := cnt_t'high;
else
cnt := cnt - 1;
end if;
end if;
end process;

Extra signals for input/output valid and friends may be needed.

Eike

 

[krby_xtrm]

have you tested this code?, because i get an an error concerning the
left and right of the downto >> my compiler says that it should be
constant : data_in(<constant> downto 0) or data_in(32 downto
<constant&gt if i remember it right?


anyway thanks, i'll try to test your code asap.

-krby_xtrm

 

[Rolf Eike Beer]

Von krby_xtrm:

have you tested this code?,

No, as I wrote directly above the example.

because i get an an error concerning the
left and right of the downto >> my compiler says that it should be
constant : data_in(<constant> downto 0) or data_in(32 downto
constant&gt if i remember it right?

I have some similar code that passes my vsim/vcom.

Eike

 

[krby_xtrm]

i have tried to compile the code:
here's the error log:
Error: VHDL error at temp1.vhd(19): left bound of range must be a
constant
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0
warnings

i use Quartus-II software v5.0

here's the complete code i tested:
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity temp1 is
generic( size: integer:=32; size2:integer:=8);
port
(clk, res_n : in std_logic;
data_in : in std_logic_vector((size-1) downto 0);
data_out : buffer std_logic_vector((size2-1)downto 0));
end temp1;
architecture bhv of temp1 is
begin
process(res_n, clk)
subtype cnt_t is natural range 0 to size/size2 - 1 ;
variable cnt: cnt_t;
begin
if (res_n = '0') then
cnt := 0;
elsif rising_edge(clk) then
data_out <= data_in((cnt + 1)*size2 - 1 downto
cnt*size2);
if (cnt = 0) then
cnt := cnt_t'high;
else
cnt := cnt - 1;
end if;
end if;
end process;

end bhv;
--------------------------------------------------------

do you have a code that works the same way?

krby_xtrm

 

[Rolf Eike Beer]

Von krby_xtrm:

i have tried to compile the code:
here's the error log:
Error: VHDL error at temp1.vhd(19): left bound of range must be a
constant
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0
warnings

So it depends on the compiler.

do you have a code that works the same way?

Yes, it's more or less the same. And it's written the same way so it will
not help you.

Eike

 

[krby_xtrm]

Too bad. Anyway. At least i've tried.
If you happen to have another similar code
pls inform me.


Thank you very much.

Ciao!