data transfer design

[vittal]

HI , I am new to this group as well as verilog.
I have to design a module so that i can transfer data
from one clock domain to other clock domain. the 2 clocks are totally
asynchronous .
e.g. data coming at rate of 10MBps (Bytes per sec) has to be
transferred from
a clk domain (freq=100MHz) to domain (freq=45MHz). there is a valid
input signal
indicating whether the data coming is valid byte or not .
correspondingly we have to generate
a valid output signal.

I tried designing with a fifo , but i couldnt get how to calculate fifo
depth..
please tell me the logic for this design

Thanks ,
Vittal

 

[Jerry Johns]

the depth will correspond to the application your designing for, since
clk2 < clk1, the fifo will overflow after some time definitely - so
what you have to decide is how much you want data you want to buffer
and once it reaches a threshold, assert an xon signal that tells source
that no more data can be buffered until the fifo empties out

correct me if i'm wrong
vittal wrote:

HI , I am new to this group as well as verilog.
I have to design a module so that i can transfer data
from one clock domain to other clock domain. the 2 clocks are totally
asynchronous .
e.g. data coming at rate of 10MBps (Bytes per sec) has to be
transferred from
a clk domain (freq=100MHz) to domain (freq=45MHz). there is a valid
input signal
indicating whether the data coming is valid byte or not .
correspondingly we have to generate
a valid output signal.

I tried designing with a fifo , but i couldnt get how to calculate fifo
depth..
please tell me the logic for this design

Thanks ,
Vittal

 

[vittal]

is there any other method other than using fifo and not interrupting
the data source such that there is no data loss .
Jerry Johns wrote:

the depth will correspond to the application your designing for, since
clk2 < clk1, the fifo will overflow after some time definitely - so
what you have to decide is how much you want data you want to buffer
and once it reaches a threshold, assert an xon signal that tells source
that no more data can be buffered until the fifo empties out

correct me if i'm wrong
vittal wrote:
HI , I am new to this group as well as verilog.
I have to design a module so that i can transfer data
from one clock domain to other clock domain. the 2 clocks are totally
asynchronous .
e.g. data coming at rate of 10MBps (Bytes per sec) has to be
transferred from
a clk domain (freq=100MHz) to domain (freq=45MHz). there is a valid
input signal
indicating whether the data coming is valid byte or not .
correspondingly we have to generate
a valid output signal.

I tried designing with a fifo , but i couldnt get how to calculate fifo
depth..
please tell me the logic for this design

Thanks ,
Vittal

 

[gabor]

vittal wrote:

is there any other method other than using fifo and not interrupting
the data source such that there is no data loss .

This depends on the "10MB/s" data source on the 100 MHz clock.
Since your output clock is slower, you can only avoid the FIFO
if you can guarantee that the input Data Valid indicator is never
active for more that one cycle at a time, and that it is off for
at least two cycles between each valid cycle. If, for example
Data Valid is on for exactly one cycle every ten cycles of
100 MHz, you can treat the input as if it ran on a 10 MHz
clock (after a register with clock enable on Data Valid). Then
you would be able to generate a circuit to create a new
clock enable on the 45 MHz clock domain that would come
on for one cycle while that data was still valid.

If your average data rate is 10 MB/s, but your peak data rate is
much higher, you need to have enough storage to handle the
data while the input rate exceeds the output rate. In that
case the FIFO is really the simplest approach.

 

[vittal]

ok thats fine.
but since we dont know how much amount of data is to be transferred,
we cant decide on fifo depth ,i.e. at one or other time it will
overflow.
and if by chance if it is available but clk rates are variable (like
input clk rate
is x and output clk rate is y then we can get the depth by some way
..but after synthesisng
we get some hardwired system. it cant be used for some other clk rates
,since depth will change
and circuit has to be changed. I think so some fixed amount of fifo mem
must be included .
if any better solution please tell me..

gabor wrote:

vittal wrote:
is there any other method other than using fifo and not interrupting
the data source such that there is no data loss .

This depends on the "10MB/s" data source on the 100 MHz clock.
Since your output clock is slower, you can only avoid the FIFO
if you can guarantee that the input Data Valid indicator is never
active for more that one cycle at a time, and that it is off for
at least two cycles between each valid cycle. If, for example
Data Valid is on for exactly one cycle every ten cycles of
100 MHz, you can treat the input as if it ran on a 10 MHz
clock (after a register with clock enable on Data Valid). Then
you would be able to generate a circuit to create a new
clock enable on the 45 MHz clock domain that would come
on for one cycle while that data was still valid.

If your average data rate is 10 MB/s, but your peak data rate is
much higher, you need to have enough storage to handle the
data while the input rate exceeds the output rate. In that
case the FIFO is really the simplest approach.

 

[czeczek]

If you have uninterrupted stream of data you can try to make more than
one FIFO and multiplex data to write incoming data to particular FIFOs
one by one. In such a case you will obtain three stream of data with
rate/3 and your FIFO could have fixed size.

vittal wrote:

is there any other method other than using fifo and not interrupting
the data source such that there is no data loss .
Jerry Johns wrote:
the depth will correspond to the application your designing for, since
clk2 < clk1, the fifo will overflow after some time definitely - so
what you have to decide is how much you want data you want to buffer
and once it reaches a threshold, assert an xon signal that tells source
that no more data can be buffered until the fifo empties out

correct me if i'm wrong
vittal wrote:
HI , I am new to this group as well as verilog.
I have to design a module so that i can transfer data
from one clock domain to other clock domain. the 2 clocks are totally
asynchronous .
e.g. data coming at rate of 10MBps (Bytes per sec) has to be
transferred from
a clk domain (freq=100MHz) to domain (freq=45MHz). there is a valid
input signal
indicating whether the data coming is valid byte or not .
correspondingly we have to generate
a valid output signal.

I tried designing with a fifo , but i couldnt get how to calculate fifo
depth..
please tell me the logic for this design

Thanks ,
Vittal

 

[vittal]

you mean write every 3rd of my data byte into a fifo.Hence there will
be lesser chance of fifo overflow.

czeczek wrote:

If you have uninterrupted stream of data you can try to make more than
one FIFO and multiplex data to write incoming data to particular FIFOs
one by one. In such a case you will obtain three stream of data with
rate/3 and your FIFO could have fixed size.

vittal wrote:
is there any other method other than using fifo and not interrupting
the data source such that there is no data loss .
Jerry Johns wrote:
the depth will correspond to the application your designing for, since
clk2 < clk1, the fifo will overflow after some time definitely - so
what you have to decide is how much you want data you want to buffer
and once it reaches a threshold, assert an xon signal that tells source
that no more data can be buffered until the fifo empties out

correct me if i'm wrong
vittal wrote:
HI , I am new to this group as well as verilog.
I have to design a module so that i can transfer data
from one clock domain to other clock domain. the 2 clocks are totally
asynchronous .
e.g. data coming at rate of 10MBps (Bytes per sec) has to be
transferred from
a clk domain (freq=100MHz) to domain (freq=45MHz). there is a valid
input signal
indicating whether the data coming is valid byte or not .
correspondingly we have to generate
a valid output signal.

I tried designing with a fifo , but i couldnt get how to calculate fifo
depth..
please tell me the logic for this design

Thanks ,
Vittal

 

[czeczek]

Yes, exactly. To be more precise, reading input samples with 100Mhz
clock you can write first sample to fifo1, second sample to fifo2 and
third sample to fifo3 and repeat his process. In such a situation you
obtain three fifos which are being written with lesser rate. (33MHz).
So if you will be reading data from this fifos using 45MHz you will not
experience fifo's overflows (of course if your fifos size will be
suitable).
Of course you further processing block should be able to process some
way these three streams of data so it's depends on your application.
vittal wrote:

you mean write every 3rd of my data byte into a fifo.Hence there will
be lesser chance of fifo overflow.

czeczek wrote:
If you have uninterrupted stream of data you can try to make more than
one FIFO and multiplex data to write incoming data to particular FIFOs
one by one. In such a case you will obtain three stream of data with
rate/3 and your FIFO could have fixed size.

vittal wrote:
is there any other method other than using fifo and not interrupting
the data source such that there is no data loss .
Jerry Johns wrote:
the depth will correspond to the application your designing for, since
clk2 < clk1, the fifo will overflow after some time definitely - so
what you have to decide is how much you want data you want to buffer
and once it reaches a threshold, assert an xon signal that tells source
that no more data can be buffered until the fifo empties out

correct me if i'm wrong
vittal wrote:
HI , I am new to this group as well as verilog.
I have to design a module so that i can transfer data
from one clock domain to other clock domain. the 2 clocks are totally
asynchronous .
e.g. data coming at rate of 10MBps (Bytes per sec) has to be
transferred from
a clk domain (freq=100MHz) to domain (freq=45MHz). there is a valid
input signal
indicating whether the data coming is valid byte or not .
correspondingly we have to generate
a valid output signal.

I tried designing with a fifo , but i couldnt get how to calculate fifo
depth..
please tell me the logic for this design

Thanks ,
Vittal