Data Swtich from LPT to LCD Module!

[Johnson Lee]

Hi,
I am new to FPGA design.
I am now need to make a switch to control the signals from PC LPT to a
character LCD module.
Right now I am using Altera UP1 demo board for verfication which has
1 MAX CPLD and 1 FLEX fpga. And I write a simple code just like
D_out <= D_in
using VHDL, like a wiring from input signals to outputs.

I check the LPT signals by connecting to LCD module directly and it
shows all the information I want. But After I connecting the FPGA
interfance, it never works.
I checked the pins again and again, but no use. Then I changed the
device from MAX to FLEX, but it didn't work, neither....

I also have another code which is used to initial LCD module and
show some words, after I programed, both devices work fine.
I don't know what's wrong inside and I even change the code by using
schmatics, still not working.
Is there anything I can do to improve this ?

Thank you!

BR,
Johnson Lee

 

[Johnson Lee]

To summarise :-

Test 1: PC LPT-->FPGA-->LCD. FAILS.
Test 2: PC LPT-->CPLD-->LCD. FAILS.
Test 3: PC LPT-->LCD. No CPLD. No FPGA. Works OK.
Test 4: CPLD-->LCD. No PC. Works OK
Test 5: FPGA-->LCD. No PC. Works OK.

Is this correct?
Did you check _all_ outputs using an oscilloscope in tests 1+2?
Was the LCD connected to the same outputs in 1+2 as it was in 4+5?
Are you using the Altera Quartus development environment?
Could you post sample Quartus archive (.QAR) files?

Hi Andrew,
Yes, you are right about those 5 different tests!
And I didn't check all outputs using oscolloscope only Enable pin and
some data bits. I can see from oscilloscope when enable pin is
initiate, the data pin voltage will sweep between 3.0V to 5.0 when LCD
module is switched on, but remain 3.0V when LCD is off.
Same IO assignment in those files...
Ya, I can show you my code!
But I don't know how to do that!
Mail the .QAR to you directly?

BR,
Johnson Lee

 

[Andrew Holme]

johnsonlee@itri.org.tw (Johnson Lee) wrote

To summarise :-

Test 1: PC LPT-->FPGA-->LCD. FAILS.
Test 2: PC LPT-->CPLD-->LCD. FAILS.
Test 3: PC LPT-->LCD. No CPLD. No FPGA. Works OK.
Test 4: CPLD-->LCD. No PC. Works OK
Test 5: FPGA-->LCD. No PC. Works OK.

Is this correct?
Did you check _all_ outputs using an oscilloscope in tests 1+2?
Was the LCD connected to the same outputs in 1+2 as it was in 4+5?
Are you using the Altera Quartus development environment?
Could you post sample Quartus archive (.QAR) files?

Hi Andrew,
Yes, you are right about those 5 different tests!
And I didn't check all outputs using oscolloscope only Enable pin and
some data bits. I can see from oscilloscope when enable pin is
initiate, the data pin voltage will sweep between 3.0V to 5.0 when LCD
module is switched on, but remain 3.0V when LCD is off.

Those voltages don't sound right. The logic should swing from 0 to
Vcc. What power supply voltage are you running the CPLD / FPGA at?
5.0V or 3.3V? What power supply voltage are you running the LCD at?
You're not missing a ground connection somewhere are you?

Same IO assignment in those files...
Ya, I can show you my code!
But I don't know how to do that!
Mail the .QAR to you directly?

Can you put it on a web server and post the URL?
If not, my mail is http://www.holmea.demon.co.uk/IMG/email.gif

 

[Johnson Lee]

Hi Andrew,
Yes, you are right about those 5 different tests!
And I didn't check all outputs using oscolloscope only Enable pin and
some data bits. I can see from oscilloscope when enable pin is
initiate, the data pin voltage will sweep between 3.0V to 5.0 when LCD
module is switched on, but remain 3.0V when LCD is off.

Those voltages don't sound right. The logic should swing from 0 to
Vcc. What power supply voltage are you running the CPLD / FPGA at?
5.0V or 3.3V? What power supply voltage are you running the LCD at?
You're not missing a ground connection somewhere are you?

Same IO assignment in those files...
Ya, I can show you my code!
But I don't know how to do that!
Mail the .QAR to you directly?

Can you put it on a web server and post the URL?
If not, my mail is http://www.holmea.demon.co.uk/IMG/email.gif

Hi Andrew,
I make a call to local Altera FAE, and he replied that the Vout
should be above 2.5V for this FPGA when in high level.
LCD module needs 5V power supply, so does the FPGA demo board.
I make those measurement again this morning and I see the voltage
swing has the same frequency as the Enable signal..
Right now my LPT signals come from a Linux OS system. And the LCD
Enable is set to polling every 1 second.
I just receive a VHDL code from Altera which show me how to modify
the pins into open-drain, and I will try this tomorrow.
Also, I will sent you my .QAR files later when I come to office
tomorrow..

Thanks for your reply!

BR,
Johnson Lee

 

[Johnson Lee]

johnsonlee@itri.org.tw (Johnson Lee) wrote in message news:<8bd844de.0411080725.d52350@posting.google.com>...

Hi Andrew,
Yes, you are right about those 5 different tests!
And I didn't check all outputs using oscolloscope only Enable pin and
some data bits. I can see from oscilloscope when enable pin is
initiate, the data pin voltage will sweep between 3.0V to 5.0 when LCD
module is switched on, but remain 3.0V when LCD is off.

Those voltages don't sound right. The logic should swing from 0 to
Vcc. What power supply voltage are you running the CPLD / FPGA at?
5.0V or 3.3V? What power supply voltage are you running the LCD at?
You're not missing a ground connection somewhere are you?

Same IO assignment in those files...
Ya, I can show you my code!
But I don't know how to do that!
Mail the .QAR to you directly?

Can you put it on a web server and post the URL?
If not, my mail is http://www.holmea.demon.co.uk/IMG/email.gif

Hi Andrew,
I already find the bug.
It was the software which read the busy flag when system boot up.
I am going to modify my code.

Thanks for sharing your time with me discussing this problem!


BR,
Johnson Lee

 

[Rich Grise]

On Tue, 09 Nov 2004 22:03:51 -0800, Johnson Lee wrote:

johnsonlee@itri.org.tw (Johnson Lee) wrote in message news:<8bd844de.0411080725.d52350@posting.google.com>...
Hi Andrew,
Yes, you are right about those 5 different tests!
And I didn't check all outputs using oscolloscope only Enable pin and
some data bits. I can see from oscilloscope when enable pin is
initiate, the data pin voltage will sweep between 3.0V to 5.0 when LCD
module is switched on, but remain 3.0V when LCD is off.

Those voltages don't sound right. The logic should swing from 0 to
Vcc. What power supply voltage are you running the CPLD / FPGA at?
5.0V or 3.3V? What power supply voltage are you running the LCD at?
You're not missing a ground connection somewhere are you?

Same IO assignment in those files...
Ya, I can show you my code!
But I don't know how to do that!
Mail the .QAR to you directly?

Can you put it on a web server and post the URL?
If not, my mail is http://www.holmea.demon.co.uk/IMG/email.gif

Hi Andrew,
I already find the bug.
It was the software which read the busy flag when system boot up.
I am going to modify my code.

Thanks for sharing your time with me discussing this problem!

I can only speak for myself, but I believe others might agree with

me - coming back to the NG to say what you've done, its results,
and especially acknowledging the help, is a Good Thing.

Thanks.
Rich