B
bob
Guest
Hi I am new to programmable logic.
I got myself a Xilinx CoolRunner II CPLD design kit.
I would like to make a project to get into the swing of things.
I would like to make a data (Digital Pulse) Recorder.
Perhaps it count incoming pulses for a fixed length of time (or set by
pc) then store the count and time stamp in the CPLD or FPGA or
external memory to later be transferred to the PC
Perhaps out a serial rs232 port to the pc.
So simply a programmable logic device
Maybe some external memory
Serial interface to computer.
If storing the data is hard to do it could simply count the incoming
pulses for one minute, then transfer the data out to a pc and clear
the counter for the next cycle.
It would require that the pc be connected while acquiring data
This should only require a fast input pin and an output in ASCII
format
i.e. start and stop bits (I can convert it to rs232 with a external
max232 chip).
Does anyone have any examples (CPLD or FPGA), or web links to tutorial
type examples of such a project? in VHDL or Verilog
Martin
I got myself a Xilinx CoolRunner II CPLD design kit.
I would like to make a project to get into the swing of things.
I would like to make a data (Digital Pulse) Recorder.
Perhaps it count incoming pulses for a fixed length of time (or set by
pc) then store the count and time stamp in the CPLD or FPGA or
external memory to later be transferred to the PC
Perhaps out a serial rs232 port to the pc.
So simply a programmable logic device
Maybe some external memory
Serial interface to computer.
If storing the data is hard to do it could simply count the incoming
pulses for one minute, then transfer the data out to a pc and clear
the counter for the next cycle.
It would require that the pc be connected while acquiring data
This should only require a fast input pin and an output in ASCII
format
i.e. start and stop bits (I can convert it to rs232 with a external
max232 chip).
Does anyone have any examples (CPLD or FPGA), or web links to tutorial
type examples of such a project? in VHDL or Verilog
Martin