data hazards and the mips

[Klejmann]

Hi,

I'm a beginner in VHDL but want to build in a stall logic in the mips
(pipelined Risc processor) that indicates a LW/SW Hazard.
I thougt this problem could be solved with a stall logic like that:
----------------------------------------------------------------------------
------
stall <= '1'
when (id_ex_memread = '1' AND ((register_rs = d_register_rt) OR (register_rt
= d_register_rt))) else '0';
----------------------------------------------------------------------------
-----
register_rs, register_rt are outputs from the ifetch-stage,
d_register_rt is an output from the execute-stage

My problem is, that if a stall appears, the control register must be set to
zero.
I thought a process like that would solve the problem:

pipeline: process(clock, reset)
begin
if reset = '1' then
D_Register_WB <= "00";
D_Register_M <= "000";
D_Register_EX <= "0000";

elsif rising_edge(clock) then
if (stall = '0') then
D_Register_WB(0) <= MemtoReg ;
D_Register_WB(1) <= RegWrite ;

D_Register_M(0) <= MemWrite;
D_Register_M(1) <= MemRead;
D_Register_M(2) <= Branch;

D_Register_EX(0) <= ALUSrc;
D_Register_EX(1) <= ALUOp(0);
D_Register_EX(2) <= ALUOp(1);
D_Register_Ex(3) <= RegDst;
end if;

if (stall = '1') then
D_Register_WB <= "00";
D_Register_M <= "000";
D_Register_EX <= "0000";
end if;
end if;
end process;

Unfortunatly the stall - change will appear in the next clock cycle and not
in the active one.
Does anyone knows a solution to clear the control-register in the same
clock-cycle??

thx
Christian Klejmann

 

[Just an Illusion]

Hi Klejmann,

That is normal that stall don't take into account in your process,
firstly because it is not into the list of sensitivity, secondly because
you have design a flip-flop (with asynchronous reset), with a mux
controlled by 'stall' in front of it.

I'll suppose that you control register is D_Register_WB & D_Register_M &
D_Register_EX, don't it ?

Do you need that 'stall' interpretation was synchronous ? either you
can do that:

reset_async <= stall or reset;

pipeline: process (clock, reset_async)
begin

if reset_async = '1' then
D_Register_WB <= "00";
D_Register_M <= "000";
D_Register_EX <= "0000";

elsif rising_edge(clock) then
D_Register_WB(0) <= MemtoReg ;
D_Register_WB(1) <= RegWrite ;

D_Register_M(0) <= MemWrite;
D_Register_M(1) <= MemRead;
D_Register_M(2) <= Branch;

D_Register_EX(0) <= ALUSrc;
D_Register_EX(1) <= ALUOp(0);
D_Register_EX(2) <= ALUOp(1);
D_Register_Ex(3) <= RegDst;
end if;
end process;

-------------------

For synchronous, the code is better like

pipeline: process(clock, reset)
begin
if reset = '1' then
D_Register_WB <= "00";
D_Register_M <= "000";
D_Register_EX <= "0000";

elsif rising_edge(clock) then
if (stall = '0') then
D_Register_WB(0) <= MemtoReg ;
D_Register_WB(1) <= RegWrite ;

D_Register_M(0) <= MemWrite;
D_Register_M(1) <= MemRead;
D_Register_M(2) <= Branch;

D_Register_EX(0) <= ALUSrc;
D_Register_EX(1) <= ALUOp(0);
D_Register_EX(2) <= ALUOp(1);
D_Register_Ex(3) <= RegDst;
else
D_Register_WB <= "00";
D_Register_M <= "000";
D_Register_EX <= "0000";
end if;
end if;
end process;

It is less confusing, but that not change your problem, because you need
wait a rising edge on clock to change the values of D_Register_WB &
D_Register_M & D_Register_EX.
Problem come from the 'time' of stall generation: if at least on between
'id_ex_memread', 'register_rs' and 'register_rt' is synchronize by
'clock', then 'stall' change 'after' the rising edge of this
synchronized signal. And in pipeline process, the value is always the
old one, when process is awake by 'clock' event.
At next 'clock' rising edge, if nothing change the 'stall' value
(before), you have your expected value.

SeeYa,
JaI

Klejmann wrote:

Hi,

I'm a beginner in VHDL but want to build in a stall logic in the mips
(pipelined Risc processor) that indicates a LW/SW Hazard.
I thougt this problem could be solved with a stall logic like that:
----------------------------------------------------------------------------
------
stall <= '1'
when (id_ex_memread = '1' AND ((register_rs = d_register_rt) OR (register_rt
= d_register_rt))) else '0';
----------------------------------------------------------------------------
-----
register_rs, register_rt are outputs from the ifetch-stage,
d_register_rt is an output from the execute-stage

My problem is, that if a stall appears, the control register must be set to
zero.
I thought a process like that would solve the problem:

pipeline: process(clock, reset)
begin
if reset = '1' then
D_Register_WB <= "00";
D_Register_M <= "000";
D_Register_EX <= "0000";

elsif rising_edge(clock) then
if (stall = '0') then
D_Register_WB(0) <= MemtoReg ;
D_Register_WB(1) <= RegWrite ;

D_Register_M(0) <= MemWrite;
D_Register_M(1) <= MemRead;
D_Register_M(2) <= Branch;

D_Register_EX(0) <= ALUSrc;
D_Register_EX(1) <= ALUOp(0);
D_Register_EX(2) <= ALUOp(1);
D_Register_Ex(3) <= RegDst;
end if;

if (stall = '1') then
D_Register_WB <= "00";
D_Register_M <= "000";
D_Register_EX <= "0000";
end if;
end if;
end process;

Unfortunatly the stall - change will appear in the next clock cycle and not
in the active one.
Does anyone knows a solution to clear the control-register in the same
clock-cycle??

thx
Christian Klejmann