Data Decoding at 10 Gbit/s

[Martin Schimmelpfennig]

Hi,

I would like to design a 16 channel SERDES ASIC in 0.13ľm running at 10
Gbit/s per channel. For transmission a standard 8B/10B is to be applied. My
concern is now how to achieve real-time decoding of the 8B/10B transmission
code at 10 Gbit/s with that technology? Can that easily be achieved? What is
state-of-the-art? As far as I know the 8B/10B decoding cannot be down by a
simple lookup table because the corresponding code words depend on the
running disparity of the previous transmitted data and there is no simple
1-on-1 mapping.
Since the 8B/10B coding is a self-synchronizing (?) code (i.e. the clock can
be retrieved from the transmitted data) I would have to use a kind of clock
recovery at my SERDES input. Another question would be if a PLL at the input
is advisable or even feasible at data rates of 10 Gbit/s.

I would be very thankful if some of you could give me a hint.

Best Regards

Martin

 

[Kai Harrekilde-Petersen]

"Martin Schimmelpfennig" <quinn_the_esquimo@freenet.de> writes:

Hi,

I would like to design a 16 channel SERDES ASIC in 0.13ľm running at 10
Gbit/s per channel.

Vitesse is certainly achieving >10Gbit/s in 0.13um - ISTR that they
also have done 12.5Gbit/s. They have chips doing 10Gbit/s SERDES for
at least 2 years now, but as far as I remember, this is only 1-4
channels per chip. YMMV.

For transmission a standard 8B/10B is to be applied. My
concern is now how to achieve real-time decoding of the 8B/10B transmission
code at 10 Gbit/s with that technology? Can that easily be achieved?

It's only a 1GHz encoding/decoding rate (parallel datarate), so I
don't see why it should be a problem. Again, Some/all of Vitesse
10Gbit/s chips implement 8B/10B.

Disclaimer: I don't work Vitesse (any more).


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>

 

[Melanie Nasic]

Joseph...dismissed!


"JosephKK" <joseph2k@lanset.com> schrieb im Newsbeitrag
news76uf.60758$tV6.16869@newssvr27.news.prodigy.net...

Martin Schimmelpfennig wrote:

Hi,

I would like to design a 16 channel SERDES ASIC in 0.13ľm running at 10
Gbit/s per channel. For transmission a standard 8B/10B is to be applied.
My concern is now how to achieve real-time decoding of the 8B/10B
transmission code at 10 Gbit/s with that technology? Can that easily be
achieved? What is state-of-the-art? As far as I know the 8B/10B decoding
cannot be down by a simple lookup table because the corresponding code
words depend on the running disparity of the previous transmitted data
and
there is no simple 1-on-1 mapping.
Since the 8B/10B coding is a self-synchronizing (?) code (i.e. the clock
can be retrieved from the transmitted data) I would have to use a kind of
clock recovery at my SERDES input. Another question would be if a PLL at
the input is advisable or even feasible at data rates of 10 Gbit/s.

I would be very thankful if some of you could give me a hint.

Best Regards

Martin


Congratulations PeteS and Kai, you told this willfully ignorant SOB
graduate
student trying to get you to do his schoolwork for him to do the work
himself. Better still you gave him good paces to learn what what he
should
have found out for him self if he could been bothered to google a bit.
--
JosephKK