Data conversion: complex, real, std_logic_vector...

[eneko]

Hello, I´m new in this forum and first of all hello and thanks other
members.
I have to implement a VHDL program which uses complex numbers and I use
math_complex library which have a function called cmplx whitch can convert
a real number in a complex one.
The problem is that I need to use an std_logic_vector input, and I can´t
convert this input in real.
Can anyone help me?

Thanks for all!

 

[mike_treseler]

You can cast integer to real something like:
real_v := real(to_integer(unsigned(std_c)));
See the details below.

-- Mike Treseler

--__________________________________
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

entity std2real is
end std2real;

architecture sim of std2real is begin
-- Tue Oct 19 10:11:39 2004 Mike Treseler

what : process is
constant std_c : std_logic_vector := x"81";
variable real_v : real;
begin
real_v := real(to_integer(unsigned(std_c)));
assert real_v = real(16#81#)
report "conversion error";
wait;
end process what;
end sim;

 

[eneko]

Thanks a lot mike, I`m very pleased.