D-Flip-flop

A

Ash12

Guest
Hi,

Im looking for bit of help / advice!!!

Im desining a counter for a device and I am using flip flops to do so. Im
using a d-type flip flop then using that flip flop as a component for
other modules. The problem I am getting is when I use the flip flop as a
module I am not getting the output waveforms I am expecting. In fact Im
getting no waveforms!!

Here is the code for my flip flop:

entity dflipflop is
Port ( D : in std_logic;
Clk : in std_logic;
Q : out std_logic;
Q_bar : out std_logic);
end dflipflop;

architecture Behavioral of dflipflop is
begin
process(Clk)
begin
if (Clk'event and Clk = '1') then
Q <= D;
Q_bar <= not(D);

end if;

end process;
end Behavioral;

I then use that code as a component to generate a counter that will divide
by 2, 4, 8, and 16.

For example here is the code for my divide by 2 counter using the above
code as a component:

entity divide_by_two is
Port (Clk : in std_logic;
Clk_out : out std_logic);
end divide_by_two;

architecture Behavioral of divide_by_two is

component dflipflop is
Port ( D : in std_logic;
Clk : in std_logic;
Q : out std_logic;
Q_bar : out std_logic);
end component;

signal D : std_logic;
--signal F : std_logic;
begin

uuu: dflipflop port map(D,Clk,Clk_Out,D);

end Behavioral;

The code is compiling fine. After debuging the code I think the problem
is that my Q_bar is being equal to my D instead of the other way around
but I cannot seem to set D equal to Q_bar.

I am hoping that after looking at this for so long that it is in fact a
simple error on my part and any help would be greatly appreciated.

Please contact me at b00003716@itb.ie
 
I think if you drive D (port in) with delay it could be work. If you
have to go down to synthesys (FPGA,CPLD) you have to change strategy.


Ash12 ha scritto:
Hi,

Im looking for bit of help / advice!!!

Im desining a counter for a device and I am using flip flops to do so. Im
using a d-type flip flop then using that flip flop as a component for
other modules. The problem I am getting is when I use the flip flop as a
module I am not getting the output waveforms I am expecting. In fact Im
getting no waveforms!!

Here is the code for my flip flop:

entity dflipflop is
Port ( D : in std_logic;
Clk : in std_logic;
Q : out std_logic;
Q_bar : out std_logic);
end dflipflop;

architecture Behavioral of dflipflop is
begin
process(Clk)
begin
if (Clk'event and Clk = '1') then
Q <= D;
Q_bar <= not(D);

end if;

end process;
end Behavioral;

I then use that code as a component to generate a counter that will divide
by 2, 4, 8, and 16.

For example here is the code for my divide by 2 counter using the above
code as a component:

entity divide_by_two is
Port (Clk : in std_logic;
Clk_out : out std_logic);
end divide_by_two;

architecture Behavioral of divide_by_two is

component dflipflop is
Port ( D : in std_logic;
Clk : in std_logic;
Q : out std_logic;
Q_bar : out std_logic);
end component;

signal D : std_logic;
--signal F : std_logic;
begin

uuu: dflipflop port map(D,Clk,Clk_Out,D);

end Behavioral;

The code is compiling fine. After debuging the code I think the problem
is that my Q_bar is being equal to my D instead of the other way around
but I cannot seem to set D equal to Q_bar.

I am hoping that after looking at this for so long that it is in fact a
simple error on my part and any help would be greatly appreciated.

Please contact me at b00003716@itb.ie
Click to expand...
 
Hi,

Default value of std_logic is 'U' means uninitialize .when simulation
starts value of signal D is 'U' .And feedback logic to your divide by
2 counter is not D_Bar . So not D_Bar again gives 'U'. Hope you
understand this.

Every sequential element must have Reset / Preset. When you power on
your Filp Flop you dont know what is your output . So first Reset it
before you start any computation. Here is the code with the Reset logic
added. Simulate this code you will get the expected output...

entity dflipflop is
Port ( D : in std_logic;
Clk : in std_logic;
Reset : in std_logic;
Q : out std_logic;
Q_bar : out std_logic);
end dflipflop;


architecture Behavioral of dflipflop is
begin
process(Clk,Reset)
begin
if(Reset = '0')then
Q <= '0';
Q_bar <= '1';
elsif (Clk'event and Clk = '1') then
Q <= D;
Q_bar <= not(D);
end if;
end process;
end Behavioral;

entity divide_by_two is
Port (Clk : in std_logic;
Reset : in std_logic;
Clk_out : out std_logic);
end divide_by_two;


architecture Behavioral of divide_by_two is


component dflipflop is
Port ( D : in std_logic;
Clk : in std_logic;
Reset : in std_logic;
Q : out std_logic;
Q_bar : out std_logic);
end component;
signal D : std_logic;
--signal F : std_logic;
begin
uuu: dflipflop port map(D,Clk,Reset,Clk_Out,D);
end Behavioral;
 
"Ash12" <b00003716@itb.ie> wrote in message news:<ca984a47f429e7b0b505a5ee312bcc78@localhost.talkaboutelectronicequipment.com>...
Hi,

Im looking for bit of help / advice!!!

Im desining a counter for a device and I am using flip flops to do so. Im
using a d-type flip flop then using that flip flop as a component for
other modules. The problem I am getting is when I use the flip flop as a
module I am not getting the output waveforms I am expecting. In fact Im
getting no waveforms!!

Here is the code for my flip flop:

entity dflipflop is
Port ( D : in std_logic;
Clk : in std_logic;
Q : out std_logic;
Q_bar : out std_logic);
end dflipflop;

architecture Behavioral of dflipflop is
begin
process(Clk)
begin
if (Clk'event and Clk = '1') then
Q <= D;
Q_bar <= not(D);

end if;

end process;
end Behavioral;

I then use that code as a component to generate a counter that will divide
by 2, 4, 8, and 16.
Click to expand...
Hi,

As already suggested, your design needs a reset to be initialized, or
your simulation will never show anything but "X" coming out from the
flip-flop.

Another thought: You seem to have fallen in the same trap as I did
when I started with VHDL i.e. working on a to low abstraction level.
Describing a simple element as a D flip-flop as an entity, does not
utilize the power of VHDL.
Your complete counter may be described in a couple of lines in the
entity where it is needed. That saves you the inconvenience of
declaring a component, instantiate a number of components, mapping the
ports etc etc.

Regards, Peter
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top