Cypres PSoC devices - hdl entry for digital sections?

[Nial Stewart]

I've avoided these to date but have been approached by someone to
look at implementing the digital aspects to their design.

What's required is _very_ simple, it's basically a 24 bit up counter
feeding a down counter with half it's value when an input changes.

This is two or three lines of VHDL but I can't get their pre-defined components
to do what I need.

I don't have time to wade through reams of data sheets and have done a
quick google with no results so....

Does anyone know if it's possible to use vhdl (or verilog) to define these
digital sections?


Thanks for any pointers,


Nial.

 

[maxascent]

Nial

From the PSOC wiki page :-

PSoC resembles an FPGA in that at power up it must be configured, but thi
configuration occurs by loading instructions from the built-in Flas
memory. Unlike an FPGA, the current generation of PSoC cannot have it
digital functions reprogrammed by VHDL or Verilog, it can only b
configured with register settings.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com

 

[Nial Stewart]

From the PSOC wiki page :-
it can only be configured with register settings.

Bugger.

Thanks Jon.


Nial.

 

[rickman]

On Nov 15, 10:55 am, "maxascent"
<maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:

Nial

From the PSOC wiki page :-

PSoC resembles an FPGA in that at power up it must be configured, but this
configuration occurs by loading instructions from the built-in Flash
memory. Unlike an FPGA, the current generation of PSoC cannot have its
digital functions reprogrammed by VHDL or Verilog, it can only be
configured with register settings.

Jon        

I'm not sure where that info came from, but I have read multiple times
that the PSOC3 and PSOC5 will be programmable using Verilog. The wiki
page may be referring to the original PSoC chips.

I would suggest that the OP post this question in the forums at
psocdeveloper.com. Answers there come directly from the PSoC
engineers.

Rick

 

[-jg]

On Nov 16, 6:32 am, rickman <gnu...@gmail.com> wrote:

On Nov 15, 10:55 am, "maxascent"

maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote:
Nial

From the PSOC wiki page :-

PSoC resembles an FPGA in that at power up it must be configured, but this
configuration occurs by loading instructions from the built-in Flash
memory. Unlike an FPGA, the current generation of PSoC cannot have its
digital functions reprogrammed by VHDL or Verilog, it can only be
configured with register settings.

Jon        

I'm not sure where that info came from, but I have read multiple times
that the PSOC3 and PSOC5 will be programmable using Verilog.  The wiki
page may be referring to the original PSoC chips.

I would suggest that the OP post this question in the forums at
psocdeveloper.com.  Answers there come directly from the PSoC
engineers.

Rick

Sounds like a reply for the older PSoC series.

The new ones (PSoC3/PSoC5) can be programmed in Verilog, but it helps
to keep the fan-in below a certain ceiling (rusty here, I think it is
12 ? ) which matches the macrocells fanin.

Above that, and the reports are less readable, and the tools juggle
more, so everything gets less predictable.

-jg