Cyclone V hard memory controller

[baum]

Hi,

I try to implement a DDR3 hard memory controller in a Cyclone v device
a 5CGXFC3B6F23C7.

I created an DDR3 hard memory controller IP core with the Megawizard,
integrated the core in my design and added my design files in Quartus.

The fitter of Quartus gives following error message

Error (15332): Port SHIFTEN of cyclonev_pll_reconfig
"HeadTop:I_HeadTop|DDR3Controller:I_MemCtrlBlk|Ddr3MemCtrldr3MemCtrl_1|Ddr3MemCtrl_000

2:ddr3memctrl_inst|Ddr3MemCtrl_pll0ll0|pll1~PLL_RECONFIG" has 11
connections, but the maximum
bus width of port SHIFTEN is 9

In the file Ddr3MemCtrl_pll0 there are 11 generic_pll instances and as
far as I know the Cyclone Pll has only 9 clock outputs so I assume the
error message refers to this and barks about the two additional clock
outputs.

In the Megawizard there is no switch to select the number of clock
outputs of the hard memory controller.

I tried to synthesise the example created by the Megawizard, but the
funny thing is this example is not for the Cyclone V device I specified
in Quartus and the fitter ends with an error message too.
This time not about the Pll but about some errors with output pins.

So my question is:
Has anybody implemented successfully a design with a DDR3 hard memory
controller in a Cyclone v device or stumbled on the same error message
as above.

Btw. I use Quartus 13.1 according to Altera the latest version but IMHO
not the greatest.

Robert

 

[Adam Górski]

W dniu 2013-11-15 13:30, baum pisze:

Hi,

I try to implement a DDR3 hard memory controller in a Cyclone v device
a 5CGXFC3B6F23C7.

I created an DDR3 hard memory controller IP core with the Megawizard,
integrated the core in my design and added my design files in Quartus.

The fitter of Quartus gives following error message

Error (15332): Port SHIFTEN of cyclonev_pll_reconfig
"HeadTop:I_HeadTop|DDR3Controller:I_MemCtrlBlk|Ddr3MemCtrldr3MemCtrl_1|Ddr3MemCtrl_000

2:ddr3memctrl_inst|Ddr3MemCtrl_pll0ll0|pll1~PLL_RECONFIG" has 11
connections, but the maximum
bus width of port SHIFTEN is 9

In the file Ddr3MemCtrl_pll0 there are 11 generic_pll instances and as
far as I know the Cyclone Pll has only 9 clock outputs so I assume the
error message refers to this and barks about the two additional clock
outputs.

In the Megawizard there is no switch to select the number of clock
outputs of the hard memory controller.

I tried to synthesise the example created by the Megawizard, but the
funny thing is this example is not for the Cyclone V device I specified
in Quartus and the fitter ends with an error message too.
This time not about the Pll but about some errors with output pins.

So my question is:
Has anybody implemented successfully a design with a DDR3 hard memory
controller in a Cyclone v device or stumbled on the same error message
as above.

Btw. I use Quartus 13.1 according to Altera the latest version but IMHO
not the greatest.

Robert

Hi Robert,

Your descriptiion is too narrow to say something.
If you need my help , send to me whole example project, then I will say
something more.

Adam

 

[Theo Markettos]

baum <rf.baumgartner@arcor.de> wrote:

Hi,

I try to implement a DDR3 hard memory controller in a Cyclone v device
a 5CGXFC3B6F23C7.

I created an DDR3 hard memory controller IP core with the Megawizard,
integrated the core in my design and added my design files in Quartus.

The fitter of Quartus gives following error message

I have no experience with the CycV, but are you sure the pin attributes are
set correctly? There's usually a TCL file output by Qsys that you have to
run in Quartus to set the pin parameters before synthesis. You only have to
run it once (the settings then go into your .qsf file). If you don't do
this synthesis may fail because it incorrectly assigns pins and then fails
when those pins don't have the right properties.

Theo

 

Hi Robert,

I am also doing some work on the Cyclone V (CVEA5) and in my case Quartus software is still not able to synthesize a HMC for the FPGA that I want to use. Not even to use a soft controller with the same pins and functionality.

They are looking into this issue. In my case I need to use Quartus 13.1 since it is the only one that has support for the FPGA that I want to use.

Regards,
Filipe

On Friday, November 15, 2013 12:30:59 PM UTC, baum wrote:

Hi,



I try to implement a DDR3 hard memory controller in a Cyclone v device

a 5CGXFC3B6F23C7.



I created an DDR3 hard memory controller IP core with the Megawizard,

integrated the core in my design and added my design files in Quartus.



The fitter of Quartus gives following error message



Error (15332): Port SHIFTEN of cyclonev_pll_reconfig

"HeadTop:I_HeadTop|DDR3Controller:I_MemCtrlBlk|Ddr3MemCtrldr3MemCtrl_1|Ddr3MemCtrl_000



2:ddr3memctrl_inst|Ddr3MemCtrl_pll0ll0|pll1~PLL_RECONFIG" has 11

connections, but the maximum

bus width of port SHIFTEN is 9



In the file Ddr3MemCtrl_pll0 there are 11 generic_pll instances and as

far as I know the Cyclone Pll has only 9 clock outputs so I assume the

error message refers to this and barks about the two additional clock

outputs.



In the Megawizard there is no switch to select the number of clock

outputs of the hard memory controller.



I tried to synthesise the example created by the Megawizard, but the

funny thing is this example is not for the Cyclone V device I specified

in Quartus and the fitter ends with an error message too.

This time not about the Pll but about some errors with output pins.



So my question is:

Has anybody implemented successfully a design with a DDR3 hard memory

controller in a Cyclone v device or stumbled on the same error message

as above.



Btw. I use Quartus 13.1 according to Altera the latest version but IMHO

not the greatest.



Robert

 

在 2013年11月15日星期五UTC+8下午8时30分59秒，baum写道：

Hi,



I try to implement a DDR3 hard memory controller in a Cyclone v device

a 5CGXFC3B6F23C7.



I created an DDR3 hard memory controller IP core with the Megawizard,

integrated the core in my design and added my design files in Quartus.



The fitter of Quartus gives following error message



Error (15332): Port SHIFTEN of cyclonev_pll_reconfig

"HeadTop:I_HeadTop|DDR3Controller:I_MemCtrlBlk|Ddr3MemCtrldr3MemCtrl_1|Ddr3MemCtrl_000



2:ddr3memctrl_inst|Ddr3MemCtrl_pll0ll0|pll1~PLL_RECONFIG" has 11

connections, but the maximum

bus width of port SHIFTEN is 9



In the file Ddr3MemCtrl_pll0 there are 11 generic_pll instances and as

far as I know the Cyclone Pll has only 9 clock outputs so I assume the

error message refers to this and barks about the two additional clock

outputs.



In the Megawizard there is no switch to select the number of clock

outputs of the hard memory controller.



I tried to synthesise the example created by the Megawizard, but the

funny thing is this example is not for the Cyclone V device I specified

in Quartus and the fitter ends with an error message too.

This time not about the Pll but about some errors with output pins.



So my question is:

Has anybody implemented successfully a design with a DDR3 hard memory

controller in a Cyclone v device or stumbled on the same error message

as above.



Btw. I use Quartus 13.1 according to Altera the latest version but IMHO

not the greatest.



Robert

Hi,Robert
Did you resolve this problem? I also meet it in 5CGXFC5C6F23C7N with Quartus 13.1.My QSYS used clock bridge and mm bride.if ddr3.av0 is connected with mm bridge or ddr3.av0 is connected with cpu data,this error will happen.There is no error in Quartus 13.0.

 

在 2013年11月15日星期五UTC+8下午8时30分59秒，baum写道：

Hi,



I try to implement a DDR3 hard memory controller in a Cyclone v device

a 5CGXFC3B6F23C7.



I created an DDR3 hard memory controller IP core with the Megawizard,

integrated the core in my design and added my design files in Quartus.



The fitter of Quartus gives following error message



Error (15332): Port SHIFTEN of cyclonev_pll_reconfig

"HeadTop:I_HeadTop|DDR3Controller:I_MemCtrlBlk|Ddr3MemCtrldr3MemCtrl_1|Ddr3MemCtrl_000



2:ddr3memctrl_inst|Ddr3MemCtrl_pll0ll0|pll1~PLL_RECONFIG" has 11

connections, but the maximum

bus width of port SHIFTEN is 9



In the file Ddr3MemCtrl_pll0 there are 11 generic_pll instances and as

far as I know the Cyclone Pll has only 9 clock outputs so I assume the

error message refers to this and barks about the two additional clock

outputs.



In the Megawizard there is no switch to select the number of clock

outputs of the hard memory controller.



I tried to synthesise the example created by the Megawizard, but the

funny thing is this example is not for the Cyclone V device I specified

in Quartus and the fitter ends with an error message too.

This time not about the Pll but about some errors with output pins.



So my question is:

Has anybody implemented successfully a design with a DDR3 hard memory

controller in a Cyclone v device or stumbled on the same error message

as above.



Btw. I use Quartus 13.1 according to Altera the latest version but IMHO

not the greatest.



Robert

The same error will be happend when I tested it with DDR3 soft controller.