J
Jukka Marin
Guest
Hi,
I started learning FPGA's and Verilog and seem to run into problems every
day
I'm trying to use dual-port RAM for buffering data between a serial link
and a 32-bit CPU bus. I wrote two separate always blocks, one which
receives data from the serial link and writes it in RAM and another one
which talks to the CPU bus and allows reading of the RAM.
When I try to compile this design (using quartus ii), the compiler "never"
finishes and I believe it's trying to build the RAM array out of logic
gates. If I make the RAM small enough, the compiler succeeds (although
it takes a long time).
I did a similar thing for serial link transmission and it worked as expected
(and the compiler used real RAM for the buffer, not logic gates).
Is it wrong to access the same memory in two separate always blocks? The
serial link and the CPU bus are independent and the bus has no clock, so
I'm trying to make an async design. I'm getting no error messages about
RAM from the compiler, so I'm not sure what I'm doing wrong. (Quartus II
is usually pretty verbose, complaining about everything from unused pins
to the color of my socks, but this time it isn't helping at all.)
I would try putting the RAM stuff inside one always block, but it seems a
bit difficult to do.. (or, I still can't think FPGA - my brain always
seems to enter software mode when opening a text editor).
I'd appreciate pointers or examples which would get me unstuck. ;-)
Thanks,
-jm
I started learning FPGA's and Verilog and seem to run into problems every
day
I'm trying to use dual-port RAM for buffering data between a serial link
and a 32-bit CPU bus. I wrote two separate always blocks, one which
receives data from the serial link and writes it in RAM and another one
which talks to the CPU bus and allows reading of the RAM.
When I try to compile this design (using quartus ii), the compiler "never"
finishes and I believe it's trying to build the RAM array out of logic
gates. If I make the RAM small enough, the compiler succeeds (although
it takes a long time).
I did a similar thing for serial link transmission and it worked as expected
(and the compiler used real RAM for the buffer, not logic gates).
Is it wrong to access the same memory in two separate always blocks? The
serial link and the CPU bus are independent and the bus has no clock, so
I'm trying to make an async design. I'm getting no error messages about
RAM from the compiler, so I'm not sure what I'm doing wrong. (Quartus II
is usually pretty verbose, complaining about everything from unused pins
to the color of my socks, but this time it isn't helping at all.)
I would try putting the RAM stuff inside one always block, but it seems a
bit difficult to do.. (or, I still can't think FPGA - my brain always
seems to enter software mode when opening a text editor).
I'd appreciate pointers or examples which would get me unstuck. ;-)
Thanks,
-jm