custom memory array implementaion

[Choudhary]

Hi Group,

This is a question related to custom memory array implementaion.

I need to implement two memory array which alternate for read and
write according to the following:


Writing input into Array:
Every clock cycle a module produces a 256 bit wide data. At the end of
128 clock cycles, this data fills the memory array and no read takes
places till that point. R127 has to hold the value in first clock
cycle, Rn has to hold the value in 128-n clock cycle,R0 has to hold
the value in 128 th clock cycle.I can use a 1 to 128 (256 bit wide)
DeMux which select address decreases from 127 to 0.

Reading: Basically two arrays alternate for read and write.
A 128 to 1 (256 bit wide) MUX reads one of the data items in the array
(which was written 128 clock cycles earlier) based on MUX select
signal which is produced some where else. Reading is not in any
particular order.


Input ---------------
--/-- |DeMux| | R0 |
256 ---------------
---------------
| R1 |
---------------
:
:
---------------
| R127 |
--------------- ---|MUX| --/--
256

Now my question is :

I can steer the input into array using a 128 to 1 demux (256 bit
wide). However since I know the order in which the data goes, I don't
necessairly need to use a demux. Every clock cycle I write into R0
only.I will have shift bit associated with each data location except
at R127 called 's' in the below figure. 's' in R0 is always set to 1,
enabling that R0 can be shifted down in the next clock cycle. 's' in
the remaining locations will be set sequentailly and will be reset at
the end of 128 clock cycles to prevent unnecessary shifts.

(In the each clock cycle following, a new value will be written into
R0 and the old value in R0 will be shifted to R1; and at the same time
's' in R0 will be shifted down from 's' in R1 so that R1 can be shited
in the next clock cycle. Like wise in third clock cycle 's' in R2 is
automatically set from the 's' in R1.)


Input ---------------
--/------------| R0 |
256 ---------------
|
---------------
| R1 |
---------------
:
:
|
---------------
| R127 |
--------------- ---|MUX| --/--
200

The switching switching activity is now 127*(127+1)/2 [=n*(n+1)/2]=
127*64 ==>
64 times higher than the usual switching activity in the array.

So is this worth for saving some wires (127*256) and few gates in the
form of 1 to 128 (256 bit wide)Demux ?


Thanks for your time.

Regards,
Choudhary

 

[Jim Wu]

Why not use dual port RAMs?

Jim Wu
jimwu88NOOOSPAM@yahoo.com

kiran_krishna_choudhary@yahoo.com (Choudhary) wrote in message news:<470b6539.0308170952.1f728ed7@posting.google.com>...

Hi Group,

This is a question related to custom memory array implementaion.

I need to implement two memory array which alternate for read and
write according to the following:

 

[Martin Euredjian]

How fast is the clock?
What chip are you using?

It seems to me that you approach might be overly complex. With a bit of
control logic you could easily enable/disable shifting in what is a 256bit x
128 stage shift register. Depending on how you intend to read from this
(not entirely clear from your post) you might be able to use 8 SRL's x 256
to construct the array. You can even have a 256 bit input register that
would feed (or not) the SRL array based on your control scheme.

Depending on your clock frequency you could consider using block RAM with
intelligent control. Just as an example, if your clock (how often a 256 bit
word is available) is 1MHz, you could run the FPGA at 256MHz and use two
18Kbit SelecRAM blocks to hold the data. You'd then have a dual port random
access solution for your problem. For higher data rates you could configure
the DP RAM with a wider port, say 32 bits.

I think that, in general, it is more efficient to run FPGA's as fast as
they'll go and serialize a solution as opposed to creating huge wide
parallel paths that eat-up a lot of logic while running well below the
attainable clock rates on some of these devices.

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"




"Choudhary" <kiran_krishna_choudhary@yahoo.com> wrote in message
news:470b6539.0308170952.1f728ed7@posting.google.com...

Hi Group,

This is a question related to custom memory array implementaion.

I need to implement two memory array which alternate for read and
write according to the following:


Writing input into Array:
Every clock cycle a module produces a 256 bit wide data. At the end of
128 clock cycles, this data fills the memory array and no read takes
places till that point. R127 has to hold the value in first clock
cycle, Rn has to hold the value in 128-n clock cycle,R0 has to hold
the value in 128 th clock cycle.I can use a 1 to 128 (256 bit wide)
DeMux which select address decreases from 127 to 0.

Reading: Basically two arrays alternate for read and write.
A 128 to 1 (256 bit wide) MUX reads one of the data items in the array
(which was written 128 clock cycles earlier) based on MUX select
signal which is produced some where else. Reading is not in any
particular order.


Input ---------------
--/-- |DeMux| | R0 |
256 ---------------
---------------
| R1 |
---------------
:
:
---------------
| R127 |
--------------- ---|MUX| --/--
256

Now my question is :

I can steer the input into array using a 128 to 1 demux (256 bit
wide). However since I know the order in which the data goes, I don't
necessairly need to use a demux. Every clock cycle I write into R0
only.I will have shift bit associated with each data location except
at R127 called 's' in the below figure. 's' in R0 is always set to 1,
enabling that R0 can be shifted down in the next clock cycle. 's' in
the remaining locations will be set sequentailly and will be reset at
the end of 128 clock cycles to prevent unnecessary shifts.

(In the each clock cycle following, a new value will be written into
R0 and the old value in R0 will be shifted to R1; and at the same time
's' in R0 will be shifted down from 's' in R1 so that R1 can be shited
in the next clock cycle. Like wise in third clock cycle 's' in R2 is
automatically set from the 's' in R1.)


Input ---------------
--/------------| R0 |
256 ---------------
|
---------------
| R1 |
---------------
:
:
|
---------------
| R127 |
--------------- ---|MUX| --/--
200

The switching switching activity is now 127*(127+1)/2 [=n*(n+1)/2]=
127*64 ==
64 times higher than the usual switching activity in the array.

So is this worth for saving some wires (127*256) and few gates in the
form of 1 to 128 (256 bit wide)Demux ?


Thanks for your time.

Regards,
Choudhary