E
Eric
Guest
Hi,
I have been unable to work out how to use a user-defined type in an
entities port description. Is this possible?
I'd like to access the port signals as an array of std_logic_vector
instead of one large std_logic_vector. The way I do this at present is
a little cumbersome and I just wanted to check there isn't a better
way of achieving it. Here is what I do right now:
I use a std_logic_vector for the port description and a signal array
of std_logic_vectors inside the architecture. A for loop then ties the
two sets of signals together. So, say we implement twelve 3 bit
counters inside the entity it might look something like this:
entity counters is
port(Clock : in std_logic;
counter3port : out std_logic_vector (35 downto 0)
-- etc.
);
end counters;
architecture structure of counters is
type counter3array is array (0 to 11) of std_logic_vector (2 downto
0);
signal counter3 : counter3array;
begin
-- Translate between the userdefined type and the port type
process (counter3) begin
for i in 12 downto 1 loop
counter3port((i*3)-1 downto (i*3)-3)<=counter3(i-1);
end loop;
end process;
-- Implement the 12 three bit counters etc. here
end structure;
Is there a simpler way of accessing the port signals as an array?
Eric.
I have been unable to work out how to use a user-defined type in an
entities port description. Is this possible?
I'd like to access the port signals as an array of std_logic_vector
instead of one large std_logic_vector. The way I do this at present is
a little cumbersome and I just wanted to check there isn't a better
way of achieving it. Here is what I do right now:
I use a std_logic_vector for the port description and a signal array
of std_logic_vectors inside the architecture. A for loop then ties the
two sets of signals together. So, say we implement twelve 3 bit
counters inside the entity it might look something like this:
entity counters is
port(Clock : in std_logic;
counter3port : out std_logic_vector (35 downto 0)
-- etc.
);
end counters;
architecture structure of counters is
type counter3array is array (0 to 11) of std_logic_vector (2 downto
0);
signal counter3 : counter3array;
begin
-- Translate between the userdefined type and the port type
process (counter3) begin
for i in 12 downto 1 loop
counter3port((i*3)-1 downto (i*3)-3)<=counter3(i-1);
end loop;
end process;
-- Implement the 12 three bit counters etc. here
end structure;
Is there a simpler way of accessing the port signals as an array?
Eric.