Cube Root in Verilog RTL for Synthesis!

Hi ,
Can anyone give me some clues regarding how to implement cuberoot
function in RTL for synthesis.

thanks

 

[Keith]

john.de...@gmail.com wrote:

Hi ,
Can anyone give me some clues regarding how to implement cuberoot
function in RTL for synthesis.

thanks

Integer only? And how many bits is the input? How long can it take?

If the input is not very wide say just 16-bits and you can take 40
cycles or so, then a simple iterative approach of computing cubes may
be fine. 41^3 = 68,921 so there aren't too many potential integer cube
roots to try for a 16-bit input.