CSV pinout from Actel

[self]

Guys,

Do you know if it is possible to get a complete pinout report from the
Actel compilation flow?

I want something complete like the CSV file that comes out of the
Xilinx ISE compilation process.

I use the PHDL language to design my printed circuit boards
(phdl.sourceforge.net). I use the Xilinx CSV file to autogenerate the
device declaration in my board design.The Xilinx CSV file contains all
the pins of the package including the power, ground, special purpose
pins, used I/O and unused pins. I wrote a Xilinx2PHDL java program
that parses the CSV file into a device declaration so that I can
instantiate even large parts onto my board with very little typing.

I would like to write a similar translator for Actel FPGAs but I
cannot find a way to get a complete pinout report from my compiled
FPGA design.

Any help is greatly appreciated.

 

[Thomas Stanka]

On 27 Okt., 04:31, self <padu...@gmail.com> wrote:

Do you know if it is possible to get a complete pinout report from the
Actel compilation flow?

I want something complete like the CSV file that comes out of the
Xilinx ISE compilation process.

In ACtel Design use pin report by number (Tools-> Reports-> Resources -

Pin, select Number). It gives you a full pin report including all
pins even vcc, gnd and unused.

bye Thomas