Cross-product coverage

[Samuel]

I need design my coverage methodology where I can identify certain events
and then get the coverage of no only when those events trigger, but also all
the combination of which they occurred.

Example: I have the following events: A, B and C

I need the coverage tool to report whether or not the following occurred: A,
B, C, AB, AC, BC and ABC.

Does anyone know a good tool that helps me out with this effort?

 

[VhdlCohen]

I need design my coverage methodology where I can identify certain events
and then get the coverage of no only when those events trigger, but also all
the combination of which they occurred.

Example: I have the following events: A, B and C

I need the coverage tool to report whether or not the following occurred: A,
B, C, AB, AC, BC and ABC.

Does anyone know a good tool that helps me out with this effort?

Assertion-Based Verification is gaining popularity for the documentation of
requirements, design documentation, design verification, and functional
coverage.
If you do not have a tool that can handle PSL, you;ll have to write the
functional coverage of these sequences in HDL (this is not difficult). In PSL,
what you have can easily that as:
default clock is clk;
cover {rose(a); b}; -- covering sequence "a" followed in the next clock by "b"
cover {rose(a); b;c}; -- covering sequence "a" followed in the next clock by
"b", then "c"

Of course PSL offers more strength in the defintion and verification of design
and requirement properties. See my site for more details on PSL.
-----------------------------------------------------------------------------
Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004 isbn
0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

 

[Srinivasan Venkataramanan]

Hi,
A contemporary HVL would allow you to do this fairly easily. For instance
with Specman (E language) one could do:

event sample_now; -- emit it when A,B,C are ready to be sampled

cover sample_now is {
item A;
item B;
item C;
cross A,B,C;
};

Of-course the above code is not complete by itself. I believe VERA has
similar capabilities. As Ben ponited out, the newer Property languages such
as PSL, SVA etc. are trying to standardize the coverage spec. language, but
I guess there is a while to go before they are completely up and supported
by all tools. Recently OVL started adding similar functionalities, check out
http://www.verificationlib.orfg for more.

HTH,
Srinivasan
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com

"Samuel" <samuel@austin.rr.com> wrote in message
news:VYCbc.35574$o_.35178@fe1.texas.rr.com...

I need design my coverage methodology where I can identify certain events
and then get the coverage of no only when those events trigger, but also
all
the combination of which they occurred.

Example: I have the following events: A, B and C

I need the coverage tool to report whether or not the following occurred:
A,
B, C, AB, AC, BC and ABC.

Does anyone know a good tool that helps me out with this effort?