cross-module reference - wire?

On 2008-03-05, Yottameter <yottameter@yahoo.com> wrote:
Ok, no DC, that makes sense. That should work for you in VCS. If it's
not working, post a specific example.

snip
Click to expand...

Actually, there seems to be an issue with VCS on this point. I have
opened an issue w/ Synopsys. Thanks for the input, all!

JB

--
-----------------------------------------------
John Bleichert syborg@earthlink.net
The heat from below can burn your eyes out!!
 
Hi,
I see that writing any of the following must be valid:
assign w = bot.w;
assign bot.w = w;

Tried with vcsi and modelsim... both compile well!!!

Cheers,
Amit Dhingra

On Mar 6, 12:27 am, Yottameter <yottame...@yahoo.com> wrote:
Ok, no DC, that makes sense. That should work for you in VCS. If it's
not working, post a specific example.

John Bleichert wrote:
On 2008-03-05, Dwayne Dilbeck <ddilb...@yahoo.com> wrote:

Your posts are a bit confusing. You keep mentioning that the XMRs are for
functional simulation yet mentioning "DC" which is a synthesis tool. Do you
mean VCS?

Yes, VCS - sorry for the massive repated typo!

You can access and control wires via XMR. Your ability to do so will be
limited by the tool.

initial
assign a1.b =c;
//where b is a wire, will not work. illegal

initial
assign a1.d = e;
//where d is a reg, will work.

Your will need to use force and release to control wires.
initial
force a1.b=c;
//this is legal.

The above examples work well in NCSIM.

Thanks - this gives me something to work with. Sometimes I wish I was
still working in ncsim...

JB

"John Bleichert" <syb...@earthlink.net> wrote in message
news:13sre84g4bejg13@corp.supernews.com...

Hello All

Can one "assign" to a wire in another, instantiated module? Or is a
wire not a valid cross-module reference?

assign reg_1 = module1.wire1;

I'm getting cross-module reference errors in DC and I'm not sure why.

Thanks,

JB

PS: This is difficult to search for, all I get are system verilog
hits...

--
-----------------------------------------------
John Bleichert syb...@earthlink.net
The heat from below can burn your eyes out!!
Click to expand...
 
Ok, no DC, that makes sense. That should work for you in VCS. If it's
not working, post a specific example.



John Bleichert wrote:
On 2008-03-05, Dwayne Dilbeck <ddilbeck@yahoo.com> wrote:

Your posts are a bit confusing. You keep mentioning that the XMRs are for
functional simulation yet mentioning "DC" which is a synthesis tool. Do you
mean VCS?


Yes, VCS - sorry for the massive repated typo!



You can access and control wires via XMR. Your ability to do so will be
limited by the tool.

initial
assign a1.b =c;
//where b is a wire, will not work. illegal


initial
assign a1.d = e;
//where d is a reg, will work.

Your will need to use force and release to control wires.
initial
force a1.b=c;
//this is legal.

The above examples work well in NCSIM.


Thanks - this gives me something to work with. Sometimes I wish I was
still working in ncsim...

JB



"John Bleichert" <syborg@earthlink.net> wrote in message
news:13sre84g4bejg13@corp.supernews.com...

Hello All

Can one "assign" to a wire in another, instantiated module? Or is a
wire not a valid cross-module reference?

assign reg_1 = module1.wire1;

I'm getting cross-module reference errors in DC and I'm not sure why.

Thanks,

JB

PS: This is difficult to search for, all I get are system verilog
hits...



--
-----------------------------------------------
John Bleichert syborg@earthlink.net
The heat from below can burn your eyes out!!
Click to expand...
 
On 2008-03-05, Dwayne Dilbeck <ddilbeck@yahoo.com> wrote:
Your posts are a bit confusing. You keep mentioning that the XMRs are for
functional simulation yet mentioning "DC" which is a synthesis tool. Do you
mean VCS?
Click to expand...
Yes, VCS - sorry for the massive repated typo!


You can access and control wires via XMR. Your ability to do so will be
limited by the tool.

initial
assign a1.b =c;
//where b is a wire, will not work. illegal


initial
assign a1.d = e;
//where d is a reg, will work.

Your will need to use force and release to control wires.
initial
force a1.b=c;
//this is legal.

The above examples work well in NCSIM.
Click to expand...
Thanks - this gives me something to work with. Sometimes I wish I was
still working in ncsim...

JB


"John Bleichert" <syborg@earthlink.net> wrote in message
news:13sre84g4bejg13@corp.supernews.com...
Hello All

Can one "assign" to a wire in another, instantiated module? Or is a
wire not a valid cross-module reference?

assign reg_1 = module1.wire1;

I'm getting cross-module reference errors in DC and I'm not sure why.

Thanks,

JB

PS: This is difficult to search for, all I get are system verilog
hits...



--
-----------------------------------------------
John Bleichert syborg@earthlink.net
The heat from below can burn your eyes out!!
Click to expand...

--
-----------------------------------------------
John Bleichert syborg@earthlink.net
The heat from below can burn your eyes out!!
 
Your posts are a bit confusing. You keep mentioning that the XMRs are for
functional simulation yet mentioning "DC" which is a synthesis tool. Do you
mean VCS?

You can access and control wires via XMR. Your ability to do so will be
limited by the tool.

initial
assign a1.b =c;
//where b is a wire, will not work. illegal


initial
assign a1.d = e;
//where d is a reg, will work.

Your will need to use force and release to control wires.
initial
force a1.b=c;
//this is legal.

The above examples work well in NCSIM.




"John Bleichert" <syborg@earthlink.net> wrote in message
news:13sre84g4bejg13@corp.supernews.com...
Hello All

Can one "assign" to a wire in another, instantiated module? Or is a
wire not a valid cross-module reference?

assign reg_1 = module1.wire1;

I'm getting cross-module reference errors in DC and I'm not sure why.

Thanks,

JB

PS: This is difficult to search for, all I get are system verilog
hits...



--
-----------------------------------------------
John Bleichert syborg@earthlink.net
The heat from below can burn your eyes out!!
Click to expand...
 
On 2008-03-04, John_H <newsgroup@johnhandwork.com> wrote:
On Mar 4, 1:03 pm, John Bleichert <syb...@earthlink.net> wrote:
Hello All

Can one "assign" to a wire in another, instantiated module? Or is a
wire not a valid cross-module reference?
snip

First, why would you want to use an assign in a different module from
the declaration?
Click to expand...
I'm trying to force/sense some signals inside a DUT from a
testbench. I really don't want to modify the DUT at all.

Thanks,

JB

--
-----------------------------------------------
John Bleichert syborg@earthlink.net
The heat from below can burn your eyes out!!
 
On 2008-03-04, Yottameter <yottameter@yahoo.com> wrote:
Usually cross module references are used in functional simulation, not
in synthesis. You would need to add a port to each module for synthesis,
otherwise how do you know the timing requirements, drive strength, load,
etc?

snip
Click to expand...

Correct - this is for functional simulation and I want to nudge/sense
nets inside a DUT we don't want to modify, in the testbench.

JB

--
-----------------------------------------------
John Bleichert syborg@earthlink.net
The heat from below can burn your eyes out!!
 
We actually use that pretty regularly - we work with a large system that
we have to divide and conquer. It's helpful to model some systems as a
'singleton', such as global signal generators that power up the chip.

However, I've never used it for synthesis...

John_H wrote:
On Mar 4, 1:03 pm, John Bleichert <syb...@earthlink.net> wrote:

Hello All

Can one "assign" to a wire in another, instantiated module? Or is a
wire not a valid cross-module reference?

assign reg_1 = module1.wire1;

I'm getting cross-module reference errors in DC and I'm not sure why.

Thanks,

JB

PS: This is difficult to search for, all I get are system verilog
hits...

--
-----------------------------------------------
John Bleichert syb...@earthlink.net
The heat from below can burn your eyes out!!


First, why would you want to use an assign in a different module from
the declaration?
Click to expand...
 
Usually cross module references are used in functional simulation, not
in synthesis. You would need to add a port to each module for synthesis,
otherwise how do you know the timing requirements, drive strength, load,
etc?

John Bleichert wrote:
Hello All

Can one "assign" to a wire in another, instantiated module? Or is a
wire not a valid cross-module reference?

assign reg_1 = module1.wire1;

I'm getting cross-module reference errors in DC and I'm not sure why.

Thanks,

JB

PS: This is difficult to search for, all I get are system verilog
hits...
Click to expand...
 
On Mar 4, 1:03 pm, John Bleichert <syb...@earthlink.net> wrote:
Hello All

Can one "assign" to a wire in another, instantiated module? Or is a
wire not a valid cross-module reference?

assign reg_1 = module1.wire1;

I'm getting cross-module reference errors in DC and I'm not sure why.

Thanks,

JB

PS: This is difficult to search for, all I get are system verilog
hits...

--
-----------------------------------------------
John Bleichert          syb...@earthlink.net
The heat from below can burn your eyes out!!
Click to expand...
First, why would you want to use an assign in a different module from
the declaration?
 
J

John Bleichert

Guest
Hello All

Can one "assign" to a wire in another, instantiated module? Or is a
wire not a valid cross-module reference?

assign reg_1 = module1.wire1;

I'm getting cross-module reference errors in DC and I'm not sure why.

Thanks,

JB

PS: This is difficult to search for, all I get are system verilog
hits...



--
-----------------------------------------------
John Bleichert syborg@earthlink.net
The heat from below can burn your eyes out!!
 
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