Cross-hierarchical upward name references

[Evan Lavelle]

Is the code below valid? The line 'a.i = 0' attempts to do an upward
name reference to a variable in another branch of the name tree, but
the reference needs to go one level up, and then one level down.

There are 3 modules here: a single top-level module, 'test', which
instantiates one copy each of 'a' and 'b'. This reference is made from
module scope in b, and tries to access a variable in a, without using
the full hierarchical name.

The LRM doesn't seem very clear on this, but point (b) on p194, on
upward referencing, does say "if found, the item name shall be
resolved from that scope" which implies, to me, that you can start
going down again from the new scope. cver complains that this is an
error, but various other simulators don't.

Thanks -

Evan

==========================================
module a;
reg i;
endmodule

module b;
initial begin
a.i = 0;
c;
end
task c;
$display("hello world!");
endtask
endmodule

module test;
a a();
b b();
endmodule

 

Evan Lavelle wrote:

Is the code below valid? The line 'a.i = 0' attempts to do an upward
name reference to a variable in another branch of the name tree, but
the reference needs to go one level up, and then one level down.
....
The LRM doesn't seem very clear on this, but point (b) on p194, on
upward referencing, does say "if found, the item name shall be
resolved from that scope" which implies, to me, that you can start
going down again from the new scope. cver complains that this is an
error, but various other simulators don't.

Yes, it is valid. The entire description of upward name resolution
would make no sense if it weren't.

The LRM description isn't very good here. Among other things, the BNF
given in the LRM for an upward name only allows two name components,
when in fact an arbitrary number are allowed.

The ultimate test is that Verilog-XL allows it. Where the original
LRM text came from the Verilog-XL reference manual, the actual
behavior of Verilog-XL helps clarify what it meant.

 

[Evan Lavelle]

On Sun, 19 Aug 2007 09:39:39 -0700, sharp@cadence.com wrote:

Yes, it is valid. The entire description of upward name resolution
would make no sense if it weren't.

The LRM description isn't very good here. Among other things, the BNF
given in the LRM for an upward name only allows two name components,
when in fact an arbitrary number are allowed.

The ultimate test is that Verilog-XL allows it. Where the original
LRM text came from the Verilog-XL reference manual, the actual
behavior of Verilog-XL helps clarify what it meant.

Thanks Steven. Please don't retire any time soon...