cross-connection matrix

A

Andy Luotto

Guest
I am looking for the best practice to design a cross connection matrix
which connevts bit i-th of port A to bit j-th of port B, where port A
and port B are bidir vectors.
All of this under the control of a text file which connect the elements
of a matrix which are set to 1.
the first line of the matrix is the size of the vectors (A and B are
same size) in binary format
module xconnect
(
inout [15:0] port_a,
inout [15:0] port_b
);

parameter config_file = "./xcon.pat";

reg [15:0] file_array[-1:15];
integer i,j;
reg [15:0] data_reg;

integer size;

initial begin

for(i=0;i<16;i=i+1)
data_reg <= 1'bz;

$readmemb(config_file, file_array,-1,15);

/* Size is the nr of the higher port to be considered in the
connection */
size = file_array[-1];
$display("***I: xconnect: Port nr=%0d",size);
end

always@(port_b)
begin
for(i=0;i<size;i=i+1)
begin
for(j=0;j<size;j=j+1)
if (file_array[j] == 1)
begin
data_reg <= port_b[j];
end
end
end

assign port_a = data_reg;

endmodule

A sample pattern file

0000000000010000
0000000100000000
0000001000000000
0000010000000000
0000100000000000
0001000000000000
0010000000000000
0100000000000000
1000000000000000
0000000000000001
0000000000000010
0000000000000100
0000000000001000
0000000000010000
0000000000100000
0000000001000000
0000000010000000

shows a 16x16 matrix where port_a is supposed to be connected to
port_b[j+8]

Is this implementation correct? Does anybody see any drawback?

I am scary that this module has a kind of 'preferred direction'
embedded since port_b is in the sensitivty list of the process the
assign port_b to port_a

What is confusing me is probably due to my mis-understanding about how
verilog models bidirectional signals

Any comment on this is very welcome
 
"Andy Luotto" <andyluotto@excite.com> a écrit dans le message de news:
1158742796.424596.81390@i42g2000cwa.googlegroups.com...
I am looking for the best practice to design a cross connection matrix
which connevts bit i-th of port A to bit j-th of port B, where port A
and port B are bidir vectors.
All of this under the control of a text file which connect the elements
of a matrix which are set to 1.
the first line of the matrix is the size of the vectors (A and B are
same size) in binary format
module xconnect
(
inout [15:0] port_a,
inout [15:0] port_b
);

parameter config_file = "./xcon.pat";

reg [15:0] file_array[-1:15];
integer i,j;
reg [15:0] data_reg;

integer size;

initial begin

for(i=0;i<16;i=i+1)
data_reg <= 1'bz;

$readmemb(config_file, file_array,-1,15);

/* Size is the nr of the higher port to be considered in the
connection */
size = file_array[-1];
$display("***I: xconnect: Port nr=%0d",size);
end

always@(port_b)
begin
for(i=0;i<size;i=i+1)
begin
for(j=0;j<size;j=j+1)
if (file_array[j] == 1)
begin
data_reg <= port_b[j];
end
end
end

assign port_a = data_reg;

endmodule

A sample pattern file

0000000000010000
0000000100000000
0000001000000000
0000010000000000
0000100000000000
0001000000000000
0010000000000000
0100000000000000
1000000000000000
0000000000000001
0000000000000010
0000000000000100
0000000000001000
0000000000010000
0000000000100000
0000000001000000
0000000010000000

shows a 16x16 matrix where port_a is supposed to be connected to
port_b[j+8]

Is this implementation correct? Does anybody see any drawback?

I am scary that this module has a kind of 'preferred direction'
embedded since port_b is in the sensitivty list of the process the
assign port_b to port_a

What is confusing me is probably due to my mis-understanding about how
verilog models bidirectional signals

Any comment on this is very welcome
Click to expand...

This code should do what you expect:module xconnect
(
inout [15:0] port_a,
inout [15:0] port_b
);

parameter config_file = "xcon.pat";

reg [15:0] file_array[-1:15];

integer size;

initial begin

$readmemb(config_file, file_array,-1,15);

/* Size is the nr of the higher port to be considered in the
connection */
size = file_array[-1];
$display("***I: xconnect: Port nr=%0d",size);
end

function [15:0] matrix;
input [15:0] port;
integer i,j;

begin
for(i=0;i<size;i=i+1)
for(j=0;j<size;j=j+1)
if (file_array[j] == 1)
matrix = port[j];
end
endfunction

assign port_a = matrix(port_b);
assign port_b = matrix(port_a);

endmodule

Serge
 
Thanks Serge for looking into this

I am realizing that using tranifs will do a better job since it
preserve both sterength and bi-directionality

what do you think?

cheers
 
"Andy Luotto" <andyluotto@excite.com> a écrit dans le message de news:
1158762895.970484.144750@m7g2000cwm.googlegroups.com...
Thanks Serge for looking into this

I am realizing that using tranifs will do a better job since it
preserve both sterength and bi-directionality

what do you think?

cheers
Click to expand...
Yes but how will describe a file based connectivity?
Serge
 
Serge Bédikian ha scritto:

"Andy Luotto" <andyluotto@excite.com> a écrit dans le message de news:
1158762895.970484.144750@m7g2000cwm.googlegroups.com...

Thanks Serge for looking into this

I am realizing that using tranifs will do a better job since it
preserve both sterength and bi-directionality

what do you think?

cheers


Yes but how will describe a file based connectivity?
Serge
Click to expand...
Hello Serge

your suggested inmplementation did not work: I think it is is due to
the fact that assigns did not preserve the strength.

I solved the problem as following (it is quick and dirty and probably
there is a better, more compact, way to do but it worked so I can move
on)

Thanks again

module xconnect
(
inout [15:0] port_a,
inout [15:0] port_b
);

parameter config_file = "./xcon.pat";

reg [15:0] ctrl_on[-1:15];
integer i,j;
integer size;

initial begin

$readmemb(config_file,ctrl_on,-1,15);

size = ctrl_on[-1];
if(size>16)
begin
$display("***E: size %0d is out of range",size);
$finish();
end
else
$display("***I: (xconnect): Port nr=%0d",size);


for(i=0;i<size;i=i+1)
for(j=0;j<size;j=j+1)
begin

if (ctrl_on[j] == 1)
begin
$display("***I: xconnect: Port#%0d connected to
Port#%0d",i,j);
// tranif1 (port_a,port_b[j],1);
end
else
begin
// tranif1 (port_a,port_b[j],0);
end
end

end

tranif1 (port_a[0], port_b[0],ctrl_on[0][0]);
tranif1 (port_a[0], port_b[1],ctrl_on[0][1]);
tranif1 (port_a[0], port_b[2],ctrl_on[0][2]);
tranif1 (port_a[0], port_b[3],ctrl_on[0][3]);
tranif1 (port_a[0], port_b[4],ctrl_on[0][4]);
tranif1 (port_a[0], port_b[5],ctrl_on[0][5]);
tranif1 (port_a[0], port_b[6],ctrl_on[0][6]);
tranif1 (port_a[0], port_b[7],ctrl_on[0][7]);
tranif1 (port_a[0], port_b[8],ctrl_on[0][8]);
tranif1 (port_a[0], port_b[9],ctrl_on[0][9]);
tranif1 (port_a[0],port_b[10],ctrl_on[0][10]);
tranif1 (port_a[0],port_b[11],ctrl_on[0][11]);
tranif1 (port_a[0],port_b[12],ctrl_on[0][12]);
tranif1 (port_a[0],port_b[13],ctrl_on[0][13]);
tranif1 (port_a[0],port_b[14],ctrl_on[0][14]);
tranif1 (port_a[0],port_b[14],ctrl_on[0][15]);

tranif1 (port_a[1], port_b[0],ctrl_on[1][0]);
tranif1 (port_a[1], port_b[1],ctrl_on[1][1]);
tranif1 (port_a[1], port_b[2],ctrl_on[1][2]);
tranif1 (port_a[1], port_b[3],ctrl_on[1][3]);
tranif1 (port_a[1], port_b[4],ctrl_on[1][4]);
tranif1 (port_a[1], port_b[5],ctrl_on[1][5]);
tranif1 (port_a[1], port_b[6],ctrl_on[1][6]);
tranif1 (port_a[1], port_b[7],ctrl_on[1][7]);
tranif1 (port_a[1], port_b[8],ctrl_on[1][8]);
tranif1 (port_a[1], port_b[9],ctrl_on[1][9]);
tranif1 (port_a[1],port_b[10],ctrl_on[1][10]);
tranif1 (port_a[1],port_b[11],ctrl_on[1][11]);
tranif1 (port_a[1],port_b[12],ctrl_on[1][12]);
tranif1 (port_a[1],port_b[13],ctrl_on[1][13]);
tranif1 (port_a[1],port_b[14],ctrl_on[1][14]);
tranif1 (port_a[1],port_b[14],ctrl_on[1][15]);

tranif1 (port_a[2], port_b[0],ctrl_on[2][0]);
tranif1 (port_a[2], port_b[1],ctrl_on[2][1]);
tranif1 (port_a[2], port_b[2],ctrl_on[2][2]);
tranif1 (port_a[2], port_b[3],ctrl_on[2][3]);
tranif1 (port_a[2], port_b[4],ctrl_on[2][4]);
tranif1 (port_a[2], port_b[5],ctrl_on[2][5]);
tranif1 (port_a[2], port_b[6],ctrl_on[2][6]);
tranif1 (port_a[2], port_b[7],ctrl_on[2][7]);
tranif1 (port_a[2], port_b[8],ctrl_on[2][8]);
tranif1 (port_a[2], port_b[9],ctrl_on[2][9]);
tranif1 (port_a[2],port_b[10],ctrl_on[2][10]);
tranif1 (port_a[2],port_b[11],ctrl_on[2][11]);
tranif1 (port_a[2],port_b[12],ctrl_on[2][12]);
tranif1 (port_a[2],port_b[13],ctrl_on[2][13]);
tranif1 (port_a[2],port_b[14],ctrl_on[2][14]);
tranif1 (port_a[2],port_b[14],ctrl_on[2][15]);

tranif1 (port_a[3], port_b[0],ctrl_on[3][0]);
tranif1 (port_a[3], port_b[1],ctrl_on[3][1]);
tranif1 (port_a[3], port_b[2],ctrl_on[3][2]);
tranif1 (port_a[3], port_b[3],ctrl_on[3][3]);
tranif1 (port_a[3], port_b[4],ctrl_on[3][4]);
tranif1 (port_a[3], port_b[5],ctrl_on[3][5]);
tranif1 (port_a[3], port_b[6],ctrl_on[3][6]);
tranif1 (port_a[3], port_b[7],ctrl_on[3][7]);
tranif1 (port_a[3], port_b[8],ctrl_on[3][8]);
tranif1 (port_a[3], port_b[9],ctrl_on[3][9]);
tranif1 (port_a[3],port_b[10],ctrl_on[3][10]);
tranif1 (port_a[3],port_b[11],ctrl_on[3][11]);
tranif1 (port_a[3],port_b[12],ctrl_on[3][12]);
tranif1 (port_a[3],port_b[13],ctrl_on[3][13]);
tranif1 (port_a[3],port_b[14],ctrl_on[3][14]);
tranif1 (port_a[3],port_b[15],ctrl_on[3][15]);

cut ... cut

tranif1 (port_a[15], port_b[0],ctrl_on[15][0]);
tranif1 (port_a[15], port_b[1],ctrl_on[15][1]);
tranif1 (port_a[15], port_b[2],ctrl_on[15][2]);
tranif1 (port_a[15], port_b[3],ctrl_on[15][3]);
tranif1 (port_a[15], port_b[4],ctrl_on[15][4]);
tranif1 (port_a[15], port_b[5],ctrl_on[15][5]);
tranif1 (port_a[15], port_b[6],ctrl_on[15][6]);
tranif1 (port_a[15], port_b[7],ctrl_on[15][7]);
tranif1 (port_a[15], port_b[8],ctrl_on[15][8]);
tranif1 (port_a[15], port_b[9],ctrl_on[15][9]);
tranif1 (port_a[15],port_b[10],ctrl_on[15][10]);
tranif1 (port_a[15],port_b[11],ctrl_on[15][11]);
tranif1 (port_a[15],port_b[12],ctrl_on[15][12]);
tranif1 (port_a[15],port_b[13],ctrl_on[15][13]);
tranif1 (port_a[15],port_b[14],ctrl_on[15][14]);
tranif1 (port_a[15],port_b[15],ctrl_on[15][15]);

endmodule
 
"Andy Luotto" <andyluotto@excite.com> a écrit dans le message de news:
1158768640.277008.298990@h48g2000cwc.googlegroups.com...

Serge Bédikian ha scritto:

"Andy Luotto" <andyluotto@excite.com> a écrit dans le message de news:
1158762895.970484.144750@m7g2000cwm.googlegroups.com...

Thanks Serge for looking into this

I am realizing that using tranifs will do a better job since it
preserve both sterength and bi-directionality

what do you think?

cheers


Yes but how will describe a file based connectivity?
Serge
Click to expand...
Hello Serge

your suggested inmplementation did not work: I think it is is due to
the fact that assigns did not preserve the strength.

I solved the problem as following (it is quick and dirty and probably
there is a better, more compact, way to do but it worked so I can move
on)

Thanks again

module xconnect
(
inout [15:0] port_a,
inout [15:0] port_b
);

parameter config_file = "./xcon.pat";

reg [15:0] ctrl_on[-1:15];
integer i,j;
integer size;

initial begin

$readmemb(config_file,ctrl_on,-1,15);

size = ctrl_on[-1];
if(size>16)
begin
$display("***E: size %0d is out of range",size);
$finish();
end
else
$display("***I: (xconnect): Port nr=%0d",size);


for(i=0;i<size;i=i+1)
for(j=0;j<size;j=j+1)
begin

if (ctrl_on[j] == 1)
begin
$display("***I: xconnect: Port#%0d connected to
Port#%0d",i,j);
// tranif1 (port_a,port_b[j],1);
end
else
begin
// tranif1 (port_a,port_b[j],0);
end
end

end

tranif1 (port_a[0], port_b[0],ctrl_on[0][0]);
tranif1 (port_a[0], port_b[1],ctrl_on[0][1]);
tranif1 (port_a[0], port_b[2],ctrl_on[0][2]);
tranif1 (port_a[0], port_b[3],ctrl_on[0][3]);
tranif1 (port_a[0], port_b[4],ctrl_on[0][4]);
tranif1 (port_a[0], port_b[5],ctrl_on[0][5]);
tranif1 (port_a[0], port_b[6],ctrl_on[0][6]);
tranif1 (port_a[0], port_b[7],ctrl_on[0][7]);
tranif1 (port_a[0], port_b[8],ctrl_on[0][8]);
tranif1 (port_a[0], port_b[9],ctrl_on[0][9]);
tranif1 (port_a[0],port_b[10],ctrl_on[0][10]);
tranif1 (port_a[0],port_b[11],ctrl_on[0][11]);
tranif1 (port_a[0],port_b[12],ctrl_on[0][12]);
tranif1 (port_a[0],port_b[13],ctrl_on[0][13]);
tranif1 (port_a[0],port_b[14],ctrl_on[0][14]);
tranif1 (port_a[0],port_b[14],ctrl_on[0][15]);

tranif1 (port_a[1], port_b[0],ctrl_on[1][0]);
tranif1 (port_a[1], port_b[1],ctrl_on[1][1]);
tranif1 (port_a[1], port_b[2],ctrl_on[1][2]);
tranif1 (port_a[1], port_b[3],ctrl_on[1][3]);
tranif1 (port_a[1], port_b[4],ctrl_on[1][4]);
tranif1 (port_a[1], port_b[5],ctrl_on[1][5]);
tranif1 (port_a[1], port_b[6],ctrl_on[1][6]);
tranif1 (port_a[1], port_b[7],ctrl_on[1][7]);
tranif1 (port_a[1], port_b[8],ctrl_on[1][8]);
tranif1 (port_a[1], port_b[9],ctrl_on[1][9]);
tranif1 (port_a[1],port_b[10],ctrl_on[1][10]);
tranif1 (port_a[1],port_b[11],ctrl_on[1][11]);
tranif1 (port_a[1],port_b[12],ctrl_on[1][12]);
tranif1 (port_a[1],port_b[13],ctrl_on[1][13]);
tranif1 (port_a[1],port_b[14],ctrl_on[1][14]);
tranif1 (port_a[1],port_b[14],ctrl_on[1][15]);

tranif1 (port_a[2], port_b[0],ctrl_on[2][0]);
tranif1 (port_a[2], port_b[1],ctrl_on[2][1]);
tranif1 (port_a[2], port_b[2],ctrl_on[2][2]);
tranif1 (port_a[2], port_b[3],ctrl_on[2][3]);
tranif1 (port_a[2], port_b[4],ctrl_on[2][4]);
tranif1 (port_a[2], port_b[5],ctrl_on[2][5]);
tranif1 (port_a[2], port_b[6],ctrl_on[2][6]);
tranif1 (port_a[2], port_b[7],ctrl_on[2][7]);
tranif1 (port_a[2], port_b[8],ctrl_on[2][8]);
tranif1 (port_a[2], port_b[9],ctrl_on[2][9]);
tranif1 (port_a[2],port_b[10],ctrl_on[2][10]);
tranif1 (port_a[2],port_b[11],ctrl_on[2][11]);
tranif1 (port_a[2],port_b[12],ctrl_on[2][12]);
tranif1 (port_a[2],port_b[13],ctrl_on[2][13]);
tranif1 (port_a[2],port_b[14],ctrl_on[2][14]);
tranif1 (port_a[2],port_b[14],ctrl_on[2][15]);

tranif1 (port_a[3], port_b[0],ctrl_on[3][0]);
tranif1 (port_a[3], port_b[1],ctrl_on[3][1]);
tranif1 (port_a[3], port_b[2],ctrl_on[3][2]);
tranif1 (port_a[3], port_b[3],ctrl_on[3][3]);
tranif1 (port_a[3], port_b[4],ctrl_on[3][4]);
tranif1 (port_a[3], port_b[5],ctrl_on[3][5]);
tranif1 (port_a[3], port_b[6],ctrl_on[3][6]);
tranif1 (port_a[3], port_b[7],ctrl_on[3][7]);
tranif1 (port_a[3], port_b[8],ctrl_on[3][8]);
tranif1 (port_a[3], port_b[9],ctrl_on[3][9]);
tranif1 (port_a[3],port_b[10],ctrl_on[3][10]);
tranif1 (port_a[3],port_b[11],ctrl_on[3][11]);
tranif1 (port_a[3],port_b[12],ctrl_on[3][12]);
tranif1 (port_a[3],port_b[13],ctrl_on[3][13]);
tranif1 (port_a[3],port_b[14],ctrl_on[3][14]);
tranif1 (port_a[3],port_b[15],ctrl_on[3][15]);

cut ... cut

tranif1 (port_a[15], port_b[0],ctrl_on[15][0]);
tranif1 (port_a[15], port_b[1],ctrl_on[15][1]);
tranif1 (port_a[15], port_b[2],ctrl_on[15][2]);
tranif1 (port_a[15], port_b[3],ctrl_on[15][3]);
tranif1 (port_a[15], port_b[4],ctrl_on[15][4]);
tranif1 (port_a[15], port_b[5],ctrl_on[15][5]);
tranif1 (port_a[15], port_b[6],ctrl_on[15][6]);
tranif1 (port_a[15], port_b[7],ctrl_on[15][7]);
tranif1 (port_a[15], port_b[8],ctrl_on[15][8]);
tranif1 (port_a[15], port_b[9],ctrl_on[15][9]);
tranif1 (port_a[15],port_b[10],ctrl_on[15][10]);
tranif1 (port_a[15],port_b[11],ctrl_on[15][11]);
tranif1 (port_a[15],port_b[12],ctrl_on[15][12]);
tranif1 (port_a[15],port_b[13],ctrl_on[15][13]);
tranif1 (port_a[15],port_b[14],ctrl_on[15][14]);
tranif1 (port_a[15],port_b[15],ctrl_on[15][15]);

endmodule

Then you could try a generate statement if you are using Verilog 2001

genvar i,j;

generate
for(i=0;i<16;i=i+1)
begin:iloop
for(j=0;j<16;j=j+1)
begin:jloop
tranif1 t1 (port_a,port_b[j],file_array[j]);
end
end
endgenerate
 
Andy Luotto wrote:
I am realizing that using tranifs will do a better job since it
preserve both sterength and bi-directionality
Click to expand...
There is no way to write your own model for a passive bidirectional
switch in Verilog. The typical attempt ends up with drivers both
directions. These form a closed loop, which latches up. Other
approaches have other problems.

To make this work, you need to use the built-in tranifs.
 
sharp@cadence.com ha scritto:

Andy Luotto wrote:

I am realizing that using tranifs will do a better job since it
preserve both sterength and bi-directionality

There is no way to write your own model for a passive bidirectional
switch in Verilog. The typical attempt ends up with drivers both
directions. These form a closed loop, which latches up. Other
approaches have other problems.

To make this work, you need to use the built-in tranifs.
Click to expand...
thanks all: I ended up to used tranifs with generate as suggeste by
both

which works fine

thanks again
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top