Creepage and clearance, UL 840 vs IPC 2221

[Ethan]

I am trying to reconcile PCB creepage distances between IPC2221 and UL840. In the past I have used the IPC2221 recommendations for PCB trace spacing, but have recently stumbled over UL840. To my surprise UL840 shows some extremely small clearance distances.

It looks like:
UL840 Table 9.2 calls for 0.16mm for 100V
IPC2221 Table 6.1 calls for 0.6mm for 100V

Does anyone know how to properly interpret UL840?

Thanks,

Ethan

 

[Winfield Hill]

Ethan wrote...

I am trying to reconcile PCB creepage distances between
IPC2221 and UL840. In the past I have used the IPC2221
recommendations for PCB trace spacing, but have recently
stumbled over UL840. To my surprise UL840 shows some
extremely small clearance distances.

It looks like:
UL840 Table 9.2 calls for 0.16mm for 100V
IPC2221 Table 6.1 calls for 0.6mm for 100V

Creepage distance, yes. Insulation distance,
what, 24 mils for 100V? Nah, not under a
soldermask. 2.4 inches for 10kV, OK, maybe
a little conservative. 0.37 inches, likely
a bit marginal for exposed conductors. And
totally inadequate for creepage.


--
Thanks,
- Win

 

[Winfield Hill]

Winfield Hill wrote...

Ethan wrote...

I am trying to reconcile PCB creepage distances between
IPC2221 and UL840. In the past I have used the IPC2221
recommendations for PCB trace spacing, but have recently
stumbled over UL840. To my surprise UL840 shows some
extremely small clearance distances.

It looks like:
UL840 Table 9.2 calls for 0.16mm for 100V
IPC2221 Table 6.1 calls for 0.6mm for 100V

Creepage distance, yes. Insulation distance,
what, 24 mils for 100V? Nah, not under a
soldermask. 2.4 inches for 10kV, OK, maybe
a little conservative. 0.37 inches, likely
a bit marginal for exposed conductors. And
totally inadequate for creepage.

Ethan, I haven't looked at the standards, but I
wonder, were you confounding creepage and clearance?


--
Thanks,
- Win

 

These standards are talking about creepage, which is what I am questioning. This is about creepage between two exposed pads, across the surface of the board.

My real question is why are the IPC and UL specs so different. UL840 is a little difficult to interpret, so I am likely not reading it correctly. So what is the proper way to interpret it?

What would you use for minimum spacing between pads for 100Vdc? This is a design for moderately high volume manufacturing (~100K/yr) from low cost vendors, using a no clean solder process.

Thanks for your help,

Ethan

 

The figures are correct, at least that the creepage must be withheld

Problem is that you cannot do any finepitch design then

We run into this for all our designs

Instead you do short circuit tests on all relevant, read problematic, nodes to each other

If nothing becomes dangerous or breaks into fire you have passed the test and you can ignore the creepage rules

AFAIR it is called Component Breakdown Test in the standard

It is something that takes a significant portion of our resources in a project

Cheers

Klaus

 

[Piglet]

On 28/06/2019 18:40, ethan.petersen@gmail.com wrote:

These standards are talking about creepage, which is what I am questioning. This is about creepage between two exposed pads, across the surface of the board.

My real question is why are the IPC and UL specs so different. UL840 is a little difficult to interpret, so I am likely not reading it correctly. So what is the proper way to interpret it?

What would you use for minimum spacing between pads for 100Vdc? This is a design for moderately high volume manufacturing (~100K/yr) from low cost vendors, using a no clean solder process.

Thanks for your help,

Ethan

Have you tried the Saturn PCB Toolkit software?

piglet

 

These standards are talking about creepage, which is what I am questioning. This is about creepage between two exposed pads, across the surface of the board.

My real question is why are the IPC and UL specs so different. UL840 is a little difficult to interpret, so I am likely not reading it correctly. So what is the proper way to interpret it?

What would you use for minimum spacing between pads for 100Vdc? This is a design for moderately high volume manufacturing (~100K/yr) from low cost vendors, using a no clean solder process.

Thanks for your help,

Ethan


Have you tried the Saturn PCB Toolkit software?

piglet

I just downloaded the Saturn PCB Toolkit. It looks handy. Thanks for the suggestion. The conductor spacing values it returns are straight out of IPC-2221B, no mention of UL or IEC standards.

 

On Friday, 28 June 2019 21:01:22 UTC+2, klaus.k...@gmail.com wrote:

The figures are correct, at least that the creepage must be withheld

Problem is that you cannot do any finepitch design then

We run into this for all our designs

Instead you do short circuit tests on all relevant, read problematic, nodes to each other

If nothing becomes dangerous or breaks into fire you have passed the test and you can ignore the creepage rules

AFAIR it is called Component Breakdown Test in the standard

It is something that takes a significant portion of our resources in a project

Note that I was referring to functional isolation in "hot" control circuits

The table 9.2 you refer to is creepage across insulation barriers for electric shock safety

Cheers

Klaus

 

[Winfield Hill]

klaus.kragelund@gmail.com wrote...

AFAIR it is called Component Breakdown Test in the standard
It is something that takes a significant portion of our
resources in a project

I layout various HV PCB designs, make various tests,
good. Sometimes the board later goes up in smoke.
The designs are complicated, with drivers, switches,
input and output storage caps, current and voltage
monitors. Lots of wires going all over, crossing,
parallel, some fat, thin, on both sides of the PCB.

Then I discover a fatal careless PCB clearance error,
oops, fix on the next PCB rev.

Were my design rules at fault all along? Maybe not.
In these designs, if one part or insulation-gap fails,
it can take out other parts, and they take out more.
Sometimes it's hard to see who started it, but then
you discover a bad clearance error, that must be it.


--
Thanks,
- Win

 

[Winfield Hill]

Winfield Hill wrote...

Sometimes it's hard to see who started it, but then
you discover a bad clearance error, that must be it.

Altium lets us set global trace clearances, used by
Design-Rule-Check, but that's useless for HV nets.
We need individual settings for certain nets, and
any one net needs to have different settings for
different classes or groups of other nets.




--
Thanks,
- Win

 

[Ethan Petersen]

On Saturday, June 29, 2019 at 6:10:12 PM UTC-7, Winfield Hill wrote:

Winfield Hill wrote...

Sometimes it's hard to see who started it, but then
you discover a bad clearance error, that must be it.

Altium lets us set global trace clearances, used by
Design-Rule-Check, but that's useless for HV nets.
We need individual settings for certain nets, and
any one net needs to have different settings for
different classes or groups of other nets.




--
Thanks,
- Win

How do people feel about solder mask as an insulator?

I have two takes on this:
One, it is not really intended to be an insulator, it is there to make the soldering process work right. As a result it may have voids or pin holes or thin spots that don't effect the solder process but would compromise it as an insulator. Solder mask doesn't come with a voltage breakdown rating.

Two, in practice it seems to work pretty good as an insulator. I have never actually had a problem with this, or seen a board where it would be a problem.

Like Winfield said, Altium lets you set up fairly sophisticated design rules. Trace to trace spacing can be smaller than trace to pad or pad to pad. So you can take advantage of the solder mask as an insulator.

I worry about this because this is the type of thing where small quantities of boards will all work great, but if you are designing for quanities of many thousands you will start seeing fall out, and field returns. Especially because we buy from lowest cost vendors who are only going to have process controls for solder process, and not insulating properties.

Thoughts?

 

[Chris Jones]

On 30/06/2019 11:09, Winfield Hill wrote:

Winfield Hill wrote...

Sometimes it's hard to see who started it, but then
you discover a bad clearance error, that must be it.

Altium lets us set global trace clearances, used by
Design-Rule-Check, but that's useless for HV nets.
We need individual settings for certain nets, and
any one net needs to have different settings for
different classes or groups of other nets.

You can do that in altium with net classes. Complicated to set up, but
once done it mostly prevents anyone working on the design from making
any clearance errors.

The only problem that I found was that I couldn't get it to use
different rules for bits of ground that were thick enough and well
enough earthed to pass the high current test (25A for a minute iirc) and
be classified as "protective earth" (so only requiring basic insulation
from mains) and other bits of ground that are connected to touchable
connectors and not thick enough to pass the test for a "protective
earth", so requiring reinforced or double insulation from mains. I could
only implement the same rule for all earthed tracks, so that part had to
be manually checked.

 

[Tim Williams]

IPC-2221 is ancient, and just a recommendation anyway; follow a real
regulation, like UL or IEC something or other. I'm familiar with 60950-1
offhand, which is pretty clear and reasonable on how to calculate both
distances.

There are many for various markets and products; find the one that is
applicable to your product).

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/

"Ethan" <ethan.petersen@gmail.com> wrote in message
news:5ee984eb-5004-47b6-8f98-ebdafdd45d68@googlegroups.com...
I am trying to reconcile PCB creepage distances between IPC2221 and UL840.
In the past I have used the IPC2221 recommendations for PCB trace spacing,
but have recently stumbled over UL840. To my surprise UL840 shows some
extremely small clearance distances.

It looks like:
UL840 Table 9.2 calls for 0.16mm for 100V
IPC2221 Table 6.1 calls for 0.6mm for 100V

Does anyone know how to properly interpret UL840?

Thanks,

Ethan