creating technology file (introducing a new technology)

[solmaz]

hello
I am a senior Microelectronics student working on a project that
involves creating full-custom-IC design environment for 0.7 um
technology(I have all physical layout rules, electrical rules etc. on
a PDF document) on Cadence software. I have used AMS 0.35 um
technology for my assignments and projects, and I have enough
experience on circuit design. Basically, I need to use all the data
that I have for 0.7 um technology on CDS and be able to perform
schematic entry, analog circuit simulation, layout DRC checking and
device extraction. Is it enough just to dump my existing technology
file to a text file, change it according to my data and compile it in
order to use 0.7 technology? Or what are the steps to introduce a new
technology to Cadence?

any information is greatly appreciated

note: Currently I am using CDS version 4.4.6.

regards

Memet Solmaz

 

[fogh]

Solmaz,

forget the techfile, it is just a detail. You certainly will not get a
0.7 design kit by modifying the techfile from a 0.35 kit.

-apart from the pdf, what data do you have ?
-how much time do you have to complete this design kit creation ?
-you want to support simulation flow: you need spice models
-you want to support layout flow : you need a DRC deck and an extraction
deck
The last two you should get in one form or another from the foundry.
You will need cooperation with the foundry, if you have no good contact
with the foundry, forget it: you will be better off using the MOSIS/NCSU
PDK or the cadence generic PDK.

It would be great if ruledecks and device were models were so clever to
adapt to the information declared in the ruledeck, but it is no so. The
information in the techfile is repeated in many other places with
various syntaxes and various levels of details.

solmaz wrote:

hello
I am a senior Microelectronics student working on a project that
involves creating full-custom-IC design environment for 0.7 um
technology(I have all physical layout rules, electrical rules etc. on
a PDF document) on Cadence software. I have used AMS 0.35 um
technology for my assignments and projects, and I have enough
experience on circuit design. Basically, I need to use all the data
that I have for 0.7 um technology on CDS and be able to perform
schematic entry, analog circuit simulation, layout DRC checking and
device extraction. Is it enough just to dump my existing technology
file to a text file, change it according to my data and compile it in
order to use 0.7 technology? Or what are the steps to introduce a new
technology to Cadence?

any information is greatly appreciated

note: Currently I am using CDS version 4.4.6.

regards

Memet Solmaz

 

[S. Badel]

this is really a long and hard job, and dangerous too.
you better get in touch with the foundry to get the files
from them.

however if you really need to do it yourself here are some hints.

be able to perform schematic entry, analog circuit simulation

for this you'll need to create a library with symbols for the devices
i.e NMOS, PMOS and other resistors, diodes and whatever
you need to support. this'll allow you to draw schematics.
you'll need to add CDF (component description format)
parameters for the width, length and so on.

to be able to simulate you'll need :
1. be able to create a netlist from the schematic.
information to netlist components is gathered in
the devices CDF in the simulation information section.
for example if you use spectre :
- copy to symbol view to a spectre view.
- add a CDF parameter called 'model' containing the name
of the simulation model
- in CDF simInfo under spectre section fill in
otherParameters = 'model'
instParameters = parameters of the model. should have corresponding CDF
parameters.
termOrder = order of the terminals as they are defined in the model.
2. you must have simulation models. these can be easily created
if the foundry has given you the parameters of the BSIM model.
if not then you'll have to request them as fogh said.

layout DRC checking and device extraction.

you'll need to create rules file for you verification tool, according to the
technology rules. this can be a hard job, especially if you need to
make it error-free
also the syntax of the rules files depends on what tool you target, ie
Dracula, Diva, Assura...
1. DRC rules. you need to check every rule that is specified in
the papers you have.
2. Extraction rules. You need to make rules to recognize devices
and calculate their parameters.
ie. poly over diffusion defines a transistor. the parameters are
the gate width and length and maybe the area and perimeter
of the source and drain.
3. LVS rules. You need to specify what parameters are to be
cross-checked between the layout and the schematic.
ie. transistors should have the same width and length.

 

[solmaz]

well,
actually I don't need to create a design kit from scratch, rather I am
just required to realize typical custom-IC design flow (draw
schematics and perform simulation from schematics entry,do the layout
of schematics and DRC check, perform extraction and LVS check etc.). I
mean, I don't have to create an installable design kit like NCSU CDK.

I have the following datas in PDF format:layer definitions, layout
rules, process parameters, electrical rules and hspice bsim3
parameters.
I obtained the 0.7um technology datas from a good contact in the
foundry and I have 3-4 months to do this project.

thank you

Mehmet


fogh <cad_support@skipthisandunderscores.catena.nl> wrote in message news:<4028e5af$0$8934$e4fe514c@dreader9.news.xs4all.nl>...

Solmaz,

forget the techfile, it is just a detail. You certainly will not get a
0.7 design kit by modifying the techfile from a 0.35 kit.

-apart from the pdf, what data do you have ?
-how much time do you have to complete this design kit creation ?
-you want to support simulation flow: you need spice models
-you want to support layout flow : you need a DRC deck and an extraction
deck
The last two you should get in one form or another from the foundry.
You will need cooperation with the foundry, if you have no good contact
with the foundry, forget it: you will be better off using the MOSIS/NCSU
PDK or the cadence generic PDK.

It would be great if ruledecks and device were models were so clever to
adapt to the information declared in the ruledeck, but it is no so. The
information in the techfile is repeated in many other places with
various syntaxes and various levels of details.

solmaz wrote:
hello
I am a senior Microelectronics student working on a project that
involves creating full-custom-IC design environment for 0.7 um
technology(I have all physical layout rules, electrical rules etc. on
a PDF document) on Cadence software. I have used AMS 0.35 um
technology for my assignments and projects, and I have enough
experience on circuit design. Basically, I need to use all the data
that I have for 0.7 um technology on CDS and be able to perform
schematic entry, analog circuit simulation, layout DRC checking and
device extraction. Is it enough just to dump my existing technology
file to a text file, change it according to my data and compile it in
order to use 0.7 technology? Or what are the steps to introduce a new
technology to Cadence?

any information is greatly appreciated

note: Currently I am using CDS version 4.4.6.

regards

Memet Solmaz

 

[fogh]

You have the time and the level to do this, but I agree with Stephane
that you should try to avoid this. This is a very Q&A-nitpicking process
to create a model set, and even worse with ruledecks.

If that is not enough to discourage you:
-You have MOS modelling in a more or less usable form. The next step is
to learn more about spectre syntax in general, and spectre syntax for
this model. Use "spectre -h" command and the spectre*.pdf manuals. Look
at the *.scs files in the generic PDK from cadence
-You have no usable ruledeck. Going from the physical rule description
in you manual to a divaDRC.rul is maybe not doable in the time you have.
Ask your foundry contact for file for: calibre, diva, assura, dracula,
hercules
-read the assura/diva manuals for ruledeck writers. read also the
dracula manuals, but less carefully.

From what foundry is this .7 process ?

solmaz wrote:

well,
actually I don't need to create a design kit from scratch, rather I am
just required to realize typical custom-IC design flow (draw
schematics and perform simulation from schematics entry,do the layout
of schematics and DRC check, perform extraction and LVS check etc.). I
mean, I don't have to create an installable design kit like NCSU CDK.

I have the following datas in PDF format:layer definitions, layout
rules, process parameters, electrical rules and hspice bsim3
parameters.
I obtained the 0.7um technology datas from a good contact in the
foundry and I have 3-4 months to do this project.

thank you

Mehmet


fogh <cad_support@skipthisandunderscores.catena.nl> wrote in message news:<4028e5af$0$8934$e4fe514c@dreader9.news.xs4all.nl>...

Solmaz,

forget the techfile, it is just a detail. You certainly will not get a
0.7 design kit by modifying the techfile from a 0.35 kit.

-apart from the pdf, what data do you have ?
-how much time do you have to complete this design kit creation ?
-you want to support simulation flow: you need spice models
-you want to support layout flow : you need a DRC deck and an extraction
deck
The last two you should get in one form or another from the foundry.
You will need cooperation with the foundry, if you have no good contact
with the foundry, forget it: you will be better off using the MOSIS/NCSU
PDK or the cadence generic PDK.

It would be great if ruledecks and device were models were so clever to
adapt to the information declared in the ruledeck, but it is no so. The
information in the techfile is repeated in many other places with
various syntaxes and various levels of details.

solmaz wrote:

hello
I am a senior Microelectronics student working on a project that
involves creating full-custom-IC design environment for 0.7 um
technology(I have all physical layout rules, electrical rules etc. on
a PDF document) on Cadence software. I have used AMS 0.35 um
technology for my assignments and projects, and I have enough
experience on circuit design. Basically, I need to use all the data
that I have for 0.7 um technology on CDS and be able to perform
schematic entry, analog circuit simulation, layout DRC checking and
device extraction. Is it enough just to dump my existing technology
file to a text file, change it according to my data and compile it in
order to use 0.7 technology? Or what are the steps to introduce a new
technology to Cadence?

any information is greatly appreciated

note: Currently I am using CDS version 4.4.6.

regards

Memet Solmaz