Creating HSPICE netlist without primitives cell subcircuits

[ShamShoon]

I am trying to run an HSPICE simulation from within Analog Design
Environment. The design is in a Composer Schematic imported from a
Verilog structural netlist. Since I have the Spice models for all the
primitive gates in another file, I only want the netlister to netlist
only the design instances and then I can include the file containing
all the library cells models in the model setup dialog.

However every time, the HSPICE netlister creates a separate subcircuit
for each primitive cell which conflicts with the subcircuit definition
in the library model file and aborts the simulation. I tried changing
the name of the primitive cell view from "schematic" to something else
and then put it in both the switch view and stop view lists (The
documentation says this will prevent the netlister from netlisting
those cells), however I get the error "Cannot find any info on instance
NAND2_3 ...". The same happens if I copy the schematic view of the
primitive to another view named "hspiceD" or any other name that exists
in both the switch and stop list. And if I remove the schematic view of
the primitive cell altogether and only keep the symbol view, I get the
same error.

Is there any way I can make the netlister add only the higher level of
hierarchy without adding the empty .SUBCKT and .ENDS pairs for each
primitive. The only workaround I am doing now is to create the netlist
first, then edit it externally to remove all .SUBCKT .ENDS pairs, and
then run the simulation.

I am referring here to hspiceD

I hope I've been clear describing the problem. Any help appreciated

Thanks!

 

[m]

On 15 Feb 2006 21:37:36 -0800, "ShamShoon" <mhs000@gmail.com> wrote:

I am trying to run an HSPICE simulation from within Analog Design
Environment. The design is in a Composer Schematic imported from a
Verilog structural netlist. Since I have the Spice models for all the
primitive gates in another file, I only want the netlister to netlist
only the design instances and then I can include the file containing
all the library cells models in the model setup dialog.

However every time, the HSPICE netlister creates a separate subcircuit
for each primitive cell which conflicts with the subcircuit definition
in the library model file and aborts the simulation. I tried changing
the name of the primitive cell view from "schematic" to something else
and then put it in both the switch view and stop view lists (The
documentation says this will prevent the netlister from netlisting
those cells), however I get the error "Cannot find any info on instance
NAND2_3 ...". The same happens if I copy the schematic view of the
primitive to another view named "hspiceD" or any other name that exists
in both the switch and stop list. And if I remove the schematic view of
the primitive cell altogether and only keep the symbol view, I get the
same error.

Is there any way I can make the netlister add only the higher level of
hierarchy without adding the empty .SUBCKT and .ENDS pairs for each
primitive. The only workaround I am doing now is to create the netlist
first, then edit it externally to remove all .SUBCKT .ENDS pairs, and
then run the simulation.

I am referring here to hspiceD

I hope I've been clear describing the problem. Any help appreciated

Thanks!

I am not familiar with your tool but in general schematic entry tools
have a way of putting a level property on the cells which the
netlister uses to decide when to stop netlisting. Check the
documentation of your tool to see if such a feature exists. But you
have to also add that property to all the standard cell instantiations
in your verilog sourced netlist. The import process maybe able to add
the relevant property. This is a pretty tools speficif feature which
requires you to do some RTFM. If all else fails, you can write a small
perl script to do the removal for you and call it after your
netlister. Hopefully you can automate that process.
HTH.

 

[Andrew Beckett]

On 15 Feb 2006 21:37:36 -0800, "ShamShoon" <mhs000@gmail.com> wrote:

I am trying to run an HSPICE simulation from within Analog Design
Environment. The design is in a Composer Schematic imported from a
Verilog structural netlist. Since I have the Spice models for all the
primitive gates in another file, I only want the netlister to netlist
only the design instances and then I can include the file containing
all the library cells models in the model setup dialog.

However every time, the HSPICE netlister creates a separate subcircuit
for each primitive cell which conflicts with the subcircuit definition
in the library model file and aborts the simulation. I tried changing
the name of the primitive cell view from "schematic" to something else
and then put it in both the switch view and stop view lists (The
documentation says this will prevent the netlister from netlisting
those cells), however I get the error "Cannot find any info on instance
NAND2_3 ...". The same happens if I copy the schematic view of the
primitive to another view named "hspiceD" or any other name that exists
in both the switch and stop list. And if I remove the schematic view of
the primitive cell altogether and only keep the symbol view, I get the
same error.

Is there any way I can make the netlister add only the higher level of
hierarchy without adding the empty .SUBCKT and .ENDS pairs for each
primitive. The only workaround I am doing now is to create the netlist
first, then edit it externally to remove all .SUBCKT .ENDS pairs, and
then run the simulation.

I am referring here to hspiceD

I hope I've been clear describing the problem. Any help appreciated

Thanks!

For each of the standard cells, you'd need to create a stopping view
(typically called hspiceD). This is usually just a copy of the symbol.

Then you'd have to set up the CDF so that it knows how to netlist the
component.

Tools->CDF->Edit CDF
Set the CDF Type to "Base"
Fill in the library name and cell name
Scroll down to the simulation information section and hit the Edit button.
On the form that pops up, Choose Simulator "ŁhspiceD"
Enter the subcircuit name as the componentName
namePrefix: X
termOrder: this needs to use the pin names of the symbol, in the order that
they appear in the external SPICE file.
All other fields on the siminfo form should be blank.

OK the forms.

This needs to be done for each standard cell, and then the netlister
should stop at the standard cell, and write it out as a subcircuit instance,
with the pins in the right order.

Regards,

Andrew.

 

[fogh]

Andrew Beckett wrote:

On 15 Feb 2006 21:37:36 -0800, "ShamShoon" <mhs000@gmail.com> wrote:


I am trying to run an HSPICE simulation from within Analog Design
Environment. The design is in a Composer Schematic imported from a
Verilog structural netlist. Since I have the Spice models for all the
primitive gates in another file, I only want the netlister to netlist
only the design instances and then I can include the file containing
all the library cells models in the model setup dialog.

However every time, the HSPICE netlister creates a separate subcircuit
for each primitive cell which conflicts with the subcircuit definition
in the library model file and aborts the simulation. I tried changing
the name of the primitive cell view from "schematic" to something else
and then put it in both the switch view and stop view lists (The
documentation says this will prevent the netlister from netlisting
those cells), however I get the error "Cannot find any info on instance
NAND2_3 ...". The same happens if I copy the schematic view of the
primitive to another view named "hspiceD" or any other name that exists
in both the switch and stop list. And if I remove the schematic view of
the primitive cell altogether and only keep the symbol view, I get the
same error.

Is there any way I can make the netlister add only the higher level of
hierarchy without adding the empty .SUBCKT and .ENDS pairs for each
primitive. The only workaround I am doing now is to create the netlist
first, then edit it externally to remove all .SUBCKT .ENDS pairs, and
then run the simulation.

I am referring here to hspiceD

I hope I've been clear describing the problem. Any help appreciated

Thanks!


For each of the standard cells, you'd need to create a stopping view
(typically called hspiceD). This is usually just a copy of the symbol.

Then you'd have to set up the CDF so that it knows how to netlist the
component.

Tools->CDF->Edit CDF
Set the CDF Type to "Base"
Fill in the library name and cell name
Scroll down to the simulation information section and hit the Edit button.
On the form that pops up, Choose Simulator "ŁhspiceD"
Enter the subcircuit name as the componentName
namePrefix: X
termOrder: this needs to use the pin names of the symbol, in the order that
they appear in the external SPICE file.
All other fields on the siminfo form should be blank.

OK the forms.

This needs to be done for each standard cell, and then the netlister
should stop at the standard cell, and write it out as a subcircuit instance,
with the pins in the right order.

provided you have "hspiceD" before "schematic" in the switchviewlist.

 

[ShamShoon]

This worked like a charm. Thank you very much and now I have a better
understanding of the whole purpose of CDF editor.

Andrew Beckett wrote:

For each of the standard cells, you'd need to create a stopping view
(typically called hspiceD). This is usually just a copy of the symbol.

Then you'd have to set up the CDF so that it knows how to netlist the
component.

Tools->CDF->Edit CDF
Set the CDF Type to "Base"
Fill in the library name and cell name
Scroll down to the simulation information section and hit the Edit button.
On the form that pops up, Choose Simulator "ŁhspiceD"
Enter the subcircuit name as the componentName
namePrefix: X
termOrder: this needs to use the pin names of the symbol, in the order that
they appear in the external SPICE file.
All other fields on the siminfo form should be blank.

OK the forms.

This needs to be done for each standard cell, and then the netlister
should stop at the standard cell, and write it out as a subcircuit instance,
with the pins in the right order.

Regards,

Andrew.

 

[Andrew Beckett]

On Thu, 16 Feb 2006 14:49:48 +0100, fogh
<cad_support@skipthisandunderscores.catena.nl> wrote:

provided you have "hspiceD" before "schematic" in the switchviewlist.

Well, I was assuming he didn't have a schematic - otherwise he'd have been using
that in the first place.

Anyway, the hspiceD view needs to be the first view in the view list that it
finds for any of the standard cells - otherwise it won't stop there...
There's no need to have a schematic if you don't have a schematic ;-)

Regards,

Andrew.

 

[ShamShoon]

Andrew Beckett wrote:
<snip>

Well, I was assuming he didn't have a schematic - otherwise he'd have been using
that in the first place.

Since the high level netlist was imported from Verilog, I had to create
a Verilog stub for each standard cell. I thought that this is the way I
can preserve proper port order since the Verilog netlist was connected
by name (e.g.: .A(net1234), ...). The Verilog stub had the same port
order as that in the spice standard cells. This caused VerilogIn to
create a schematic for each standard cell that contains only the ports
and nothing else. When I tried deleting this view, I got the
aforementioned error message. However now I know that I didn't need the
schematic I just needed the CDF info entered properly.

Anyway, the hspiceD view needs to be the first view in the view list that it
finds for any of the standard cells - otherwise it won't stop there...

Yes I knew that and it was the default that the first view is hspiceD

There's no need to have a schematic if you don't have a schematic ;-)

*sigh*

Thanks again for all the help!