Creating a vector out of other vectors

[Vazquez]

Hi,

I have the following problem:



library ieee;
use ieee.std_logic_1164.all;

entity test is
port(ep_to_send : in std_logic_vector(3 downto 0);
addr_to_send : in std_logic_vector(6 downto 0);
data_valid_to_send : in std_logic;
direction_to_send : in std_logic
);
end test;

architecture rtl of test is
signal test_vector: std_logic_vector(9 downto 0);

begin
test_vector <= (addr_to_send(4 downto 0) & ep_to_send &
data_valid_to_send);

end rtl;

Is this legal in VHDL? Will the new vector be composed correctly?

Thanks

Andres Vazquez

 

[Jan De Ceuster]

Hi,

I have the following problem:



library ieee;
use ieee.std_logic_1164.all;

entity test is
port(ep_to_send : in std_logic_vector(3 downto 0);
addr_to_send : in std_logic_vector(6 downto 0);
data_valid_to_send : in std_logic;
direction_to_send : in std_logic
);
end test;

architecture rtl of test is
signal test_vector: std_logic_vector(9 downto 0);

begin
test_vector <= (addr_to_send(4 downto 0) & ep_to_send &
data_valid_to_send);

end rtl;

Is this legal in VHDL? Will the new vector be composed correctly?

Thanks

Andres Vazquez

Yep, perfectly legal code. Just be sure that the size on the left and right are
equal. And you don't need the parenthesisses. I just prefer to use those things
as less as possible.
Your code will do the following:
test_vector(9) <= addr_to_send(4);
test_vector(8) <= addr_to_send(3);
test_vector(7) <= addr_to_send(2);
test_vector(6) <= addr_to_send(1);
test_vector(5) <= addr_to_send(0);
test_vector(4) <= ep_to_send(3);
test_vector(3) <= ep_to_send(2);
test_vector(2) <= ep_to_send(1);
test_vector(1) <= ep_to_send(0);
test_vector(0) <= data_valid_to_send;

If you would revers the range of test_vector you will do this:
test_vector(0) <= addr_to_send(4);
test_vector(1) <= addr_to_send(3);
test_vector(2) <= addr_to_send(2);
.....


kind regards,
Jan