Creating a Simple counter in Verilog

[weizbox]

I am moving onto Verilog now from VHDL due to it being too complicated
for me to start off with and not having any calsses available to go to
in order to teach me it. So far Ive been just trying to make a simple
counter that would pulse an led every second, and so far no luck. Im
getting errors left and right, when I change one thing, I get another
error, and when I fix that I seem to get others. I have no idea what
Im doing wrong, everyhting looks like it would run fine from what Ive
read. So if you can let me know what my errors are. Thank you!

CODE:

module pulse(led_o, clk50);

input clk50;
output led_o;
reg [31:0] c;

always @(posedge clk50) //Trigger on 50MHz clock
begin
if (c == 50000000) //Convert 50MHz Clock to 1Hz
<= 0;
led_o <= 1; //Turn led on
wait (50ms) //wait 50ms
led_o <= 0; //turn led off

else
c <= c + 1; //Step up c +1
end

endmodule

ERRORS:

ERROR:HDLCompilers:26 - clock.v line 12 unexpected token: '50'
ERROR:HDLCompilers:26 - clock.v line 15 expecting 'end', found 'else'
ERROR:HDLCompilers:26 - clock.v line 16 unexpected token: '<='
ERROR:HDLCompilers:26 - clock.v line 16 unexpected token: '+'
ERROR:HDLCompilers:26 - clock.v line 16 expecting 'endmodule', found
'1'
ERROR: XST failed

Ive been useing this as a reference:
http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html

I suppose it isnt very good considering how far it has gotten me. If
anyone else knows of a good online resource just to look up little
things like wait, if, begin type stuff with proper sytax let me know!


All I really want to make is a simple counter to pulse an led every
second for the time being, thats it. So if thats easy enough to post,
please go for it!

Thanks!
-Weizbox

 

[John_H]

The wait(50ms) isn't synthesizable. You need to turn the LED on at one
count (or have it on "above" a count) and have it off at the wraparound. I
show the led_o assignment outside you if/else for the counter and use a
comparison to assign a 1-bit true value to the led_o bit instead of using an
if/else for that one.

The sutherland-hdl reference is great, but as a reference, not as a learning
tool. The newsgroup has had many suggestions for good books - you can
search at places like groups.google.com.

"weizbox" <mwiesbock@gmail.com> wrote in message
news:335c6753.0409271256.78f3e933@posting.google.com...

I am moving onto Verilog now from VHDL due to it being too complicated
for me to start off with and not having any calsses available to go to
in order to teach me it. So far Ive been just trying to make a simple
counter that would pulse an led every second, and so far no luck. Im
getting errors left and right, when I change one thing, I get another
error, and when I fix that I seem to get others. I have no idea what
Im doing wrong, everyhting looks like it would run fine from what Ive
read. So if you can let me know what my errors are. Thank you!

CODE:

module pulse(led_o, clk50);

input clk50;
output led_o;
reg [25:0] c; // 2^26 = 67108864 > 50000000
always @(posedge clk50) //Trigger on 50MHz clock
begin
if (c == 50000000) //Convert 50MHz Clock to 1Hz
// begin/end needed before else if more than 1 statement
c <= 0;
else
c <= c + 1; //Step up c +1
led_o <= (c[25:21] >= 5'h15); // ~60ms until reset
end

endmodule

 

[John_H]

The led needed to be a reg (preferred) or taken outside of the always block
to an assign. The reg is prefered because some glitching might occur for a
combinatorial assign - not a big problem for a visual indicator, but why not
get in the habit of making it a clean signal?.

"John_H" <johnhandwork@mail.com> wrote in message
news:XG%5d.2$r56.1366@news-west.eli.net...

module pulse(led_o, clk50);

input clk50;
output led_o;
reg [25:0] c; // 2^26 = 67108864 > 50000000
reg led_o; // pointed out elsewhere, a reg is needed
always @(posedge clk50) //Trigger on 50MHz clock
begin
if (c == 50000000) //Convert 50MHz Clock to 1Hz
// begin/end needed before else if more than 1 statement
c <= 0;
else
c <= c + 1; //Step up c +1
led_o <= (c[25:21] >= 5'h15); // ~60ms until reset
end

endmodule