Creating a new type for STD_LOGIC_VECTOR

[Kwaj]

I would like to create a new type, bit32word, which would be a 16bit
std_logic_vector. I tried the following,

type bit32word is STD_LOGIC_VECTOR(31 DOWNTO 0);

which didn't seem to work. Any ideas??

- Kwaj

 

[Steffen Netz]

Hello Kwaj,

that the typical case for an subtype:
SUBTYPE bit32word IS std_logic_vector(31 DOWNTO 0);
SIGNAL rega : bit32word := (OTHERS=>'0');

You can even get an array of this by the array type:
TYPE romarray IS ARRAY (integer RANGE <&gt OF bit32word;
SIGNAL rom_mem : romarray(255 downto 0);

regards,

Steffen

Kwaj wrote:

I would like to create a new type, bit32word, which would be a 16bit
std_logic_vector. I tried the following,

type bit32word is STD_LOGIC_VECTOR(31 DOWNTO 0);

which didn't seem to work. Any ideas??

- Kwaj

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| Steffen Netz | phone : ( +49 ) (0)351/8823-212 |
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[Riyaz]

Try using subtype instead of type

"Kwaj" <k.oteng@student.unsw.edu.au> wrote in message
news:c77b9b$qh2$1@tomahawk.unsw.edu.au...

I would like to create a new type, bit32word, which would be a 16bit
std_logic_vector. I tried the following,

type bit32word is STD_LOGIC_VECTOR(31 DOWNTO 0);

which didn't seem to work. Any ideas??

- Kwaj

 

[Lee]

Hi,

This is array type that has different syntax with scalar type.

type bit32word is array (31 DOWNTO 0) of STD_LOGIC_VECTOR;

Try it to see if it works.

Regards,

"Riyaz" <r.a.patel@sheffield.ac.uk> wrote in message news:<c7ae4n$rhv$1@hermes.shef.ac.uk>...

Try using subtype instead of type

"Kwaj" <k.oteng@student.unsw.edu.au> wrote in message
news:c77b9b$qh2$1@tomahawk.unsw.edu.au...
I would like to create a new type, bit32word, which would be a 16bit
std_logic_vector. I tried the following,

type bit32word is STD_LOGIC_VECTOR(31 DOWNTO 0);

which didn't seem to work. Any ideas??

- Kwaj