CRC Doubts

Hello folks,

I was trying to implement a CCITT CRC-16 Calculator, the polynomial is
G(x) = X^16+X^12+X^5+1 , I was trying to give a 32 bit sequence to my
module: Unfortunately it doesnt work. I have mentioned my code below
with its test bench,I am quite ambiguious in giving input data to the
moudle in bit by bit from vector_array. Any suggestions would be
helpful

Thanks in Advance
ALI


library IEEE;
use IEEE.Std_Logic_1164.all;

--------------------------------------------------------------------------------
entity CRC16 is
--------------------------------------------------------------------------------
port
(
CLK : in std_logic; -- Input clock
RESET : in std_logic; -- Reset Signal
EN : in std_logic; -- Enable Signal
D : in std_logic; -- Data Input
Q : out std_logic_vector (15 downto 0) -- CRC Output

);
end CRC16;

--------------------------------------------------------------------------------
architecture ARCH_CRC16 of CRC16 is
--------------------------------------------------------------------------------

signal CRCREG_S: std_logic_vector (15 downto 0);

--------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------

INIT_CRCREG: process(CLK,RESET,EN)

begin
if (RESET = '1') then
CRCREG_S <= (others => '0');
elsif (CLK'EVENT and CLK = '1') then
if (EN = '1') then
CRCREG_S <= (others => '1');
end if;
end if;
end process INIT_CRCREG;
--------------------------------------------------------------------------------

CRC_CALCROCESS(CLK)

variable XOR_V : std_logic;

begin

if (CLK = '1' and CLK'event) then
XOR_V := D xor CRCREG_S(15);
CRCREG_S(12) <= XOR_V xor CRCREG_S(11);
CRCREG_S(5) <= XOR_V xor CRCREG_S(4);
CRCREG_S(0) <= XOR_V;
CRCREG_S(15 downto 13) <= CRCREG_S(14 downto 12);
CRCREG_S(11 downto 6) <= CRCREG_S(10 downto 5);
CRCREG_S(4 downto 1) <= CRCREG_S(3 downto 0);
end if;




end process CRC_CALC;
-------------------------------------------------------------------

Q <= NOT(CRCREG_S);


--------------------------------------------------------------------------------
end ARCH_CRC16;
--------------------------------------------------------------------------------
-- END OF FILE
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
--TEST BENCH:
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity tb_crc16 is
end tb_crc16;

architecture arch_tb_crc16 of tb_crc16 is

component crc16
port(
CLK : in std_logic;
RESET : in std_logic;
EN : in std_logic;
D : in std_logic;
Q : out std_logic_vector(15 downto 0) );
end component;

--------------------------------------------------------------------------------

signal CLK : std_logic;
signal RESET : std_logic;
signal EN : std_logic;
signal D : std_logic;


--------------------------------------------------------------------------------

signal Q : std_logic_vector(15 downto 0);
signal Data_in : std_logic_vector(0 to 31) :=
"01010000000000000000001100000000";
--------------------------------------------------------------------------------


begin


UUT : crc16
port map
(CLK => CLK,
RESET => RESET,
EN => EN,
D => D,
Q => Q );

--------------------------------------------------------------------------------
--Concurrent process of clock

CLK_GEN: process
begin
clk <= '0';
wait for 2 ns;
clk <= '1';
wait for 2 ns;
end process CLK_GEN;
--------------------------------------------------------------------------------

--Reset Signal

RESET <= '1','0' after 4 ns;
--------------------------------------------------------------------------------

--Enable Signal

en <= '0','1' after 8 ns;

--------------------------------------------------------------------------------
Data_inp : process is
begin
for i in data_in'range loop
D <= data_in(i);
wait until rising_edge(clk);
end loop;
end process Data_inp;

-------------------------------------------------------------------------------


end arch_tb_crc16;

configuration cfg_for_crc16 of tb_crc16 is
for arch_tb_crc16
for UUT : crc16
use entity work.crc16(arch_crc16);
end for;
end for;
end cfg_for_crc16;

 

[Mike Treseler]

jahaya@gmail.com wrote:

I was trying to implement a CCITT CRC-16 Calculator, the polynomial is
G(x) = X^16+X^12+X^5+1 , I was trying to give a 32 bit sequence to my
module: Unfortunately it doesnt work.

Init the crcreg to (others => '1') before each calculation.

For a readable answer, bit reverse the crc octets.

I have mentioned my code below
with its test bench,I am quite ambiguious in giving input data to the
moudle in bit by bit from vector_array. Any suggestions would be
helpful

Consider doing an FCS checker first.
Capture several packets with a good FCS,
and use these as constants in your testbench.
Init the crcreg to (others => '1')
and play back the packet with bit zero first
and bit seven last for each octet.
All packets should give you the same crcreg remainder
after the fcs is shifted through.

-- Mike Treseler