crazy error message

T

Team C

Guest
ERROR:HDLCompiler:25 - "C:/Documents and Settings/[username]/My
Documents/My Dropbox/Comp Arch/FinalProject/top.vf" Line 1351: Module
&lt;ALU16Verilog_MUSER_top&gt; does not have a port named <a>.
ERROR:HDLCompiler:25 - "C:/Documents and Settings/[username]/My
Documents/My Dropbox/Comp Arch/FinalProject/top.vf" Line 1352: Module
&lt;ALU16Verilog_MUSER_top&gt; does not have a port named <b>.
ERROR:HDLCompiler:25 - "C:/Documents and Settings/[username]/My
Documents/My Dropbox/Comp Arch/FinalProject/top.vf" Line 1353: Module
&lt;ALU16Verilog_MUSER_top&gt; does not have a port named &lt;op&gt;.
ERROR:HDLCompiler:25 - "C:/Documents and Settings/[username]/My
Documents/My Dropbox/Comp Arch/FinalProject/top.vf" Line 1354: Module
&lt;ALU16Verilog_MUSER_top&gt; does not have a port named &lt;r&gt;.
ERROR:HDLCompiler:25 - "C:/Documents and Settings/[username]/My
Documents/My Dropbox/Comp Arch/FinalProject/top.vf" Line 1355: Module
&lt;ALU16Verilog_MUSER_top&gt; does not have a port named &lt;zero&gt;.
ERROR:Simulator:778 - Static elaboration of top level Verilog design
unit(s) in library work failed


what does this mean?
 
On Nov 5, 10:33 am, Team C &lt;war...@rose-hulman.edu&gt; wrote:
what does this mean?
Click to expand...
It means that you should have stayed awake during the lectures.
 
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