CPLD : Generating reset signal

V

Valentin Tihomirov

Guest
Active reset is high. In passive state (nRESET) I pull signal to GND with
130k resistor. Pushing a button connects signal to 3.3vcc with 10R in
series. Signal is filtered with 0.1uF capasitor. This circuit works well in
the absence of CPLD.

After plugging power, signal is low (as expected). Pressing the button
activates reset. But RESET signal remains ~2.3v after releasing the button.
What inside CPLD prevents signal from going down? Seems that 100k-pullup
emerges at the input.

CPLD is 9572XL.
 
1. Once RESET signal is stuck at 2.3v I disconnect Reset input from signal
line (make pin floating). Voltage at the in rises to 2.4 volts. It is
strange cos core voltage is 3.3v, I do not have 2.4v in my system! Where
Xilinx CPLD generates this voltage from?


Intermediate input data for the puzzle:
That is, with RESET pin disconnected from corresponding signal I have 2.4v
at reset pin and 0.0v at reset line.
Question:
What resulting voltage do I get connecting back 0v reset (13k pull-down to
GND) 2.4v at RESET input of CPLD?

2. Connecting 0v output to 2.4v input results in the following constants:
- 0v; or
- 2.3v;
with equal probability.

Im I crazy?
 
I've got information that the CPLD uses 50k bus-holding feature. I've used
12k resistor in my reseting circuit instead of 130k and this solved the
problem. However, I turrend bus keeping off in WebPack->fitter option. It is
obusfucating. 3.3v*130/(130+50) = 2.35v I was getting when my 130k was
pulling reset down and CPLD's keeper feature pulled it up with 50k.
One thing I still do not understand is why 3.3v CPLD pulls up input to 2.4v.
 
Valentin Tihomirov wrote:
I've got information that the CPLD uses 50k bus-holding feature. I've used
12k resistor in my reseting circuit instead of 130k and this solved the
problem. However, I turrend bus keeping off in WebPack->fitter option. It is
obusfucating. 3.3v*130/(130+50) = 2.35v I was getting when my 130k was
pulling reset down and CPLD's keeper feature pulled it up with 50k.
One thing I still do not understand is why 3.3v CPLD pulls up input to 2.4v.
Click to expand...
Pinkeepers are not true resistors, but are weak N FETS (reason of
smallest die area ) They seem to make the pinkeeps using N+N FETS,
rather than N+PFETS,and the pullup is the N Source follower, so you
get a G-S drop, or appx 0.9V of threshold.
Put your meter from Pin-3.3V, and it will read 0.0V,
Put it from Pin-GND, and it reads 2.4V.
Atmel CPLD data has curves of the I-V for pinkeeps that makes
this clearer.

-jg
 
I bet the default for Inputs is either pullup or weak keeper (you have
to specifically tell the software that you don't want this or it gives
it to you).

One easy way to find out if this is the problem is to put a 10k or 5k
pullup in place of the 130k. I would never use a 130k resistor anyway.
It is so weak it is almost 'not there' in the sense that any system
noise can overcome it and reset your system.
 
Active reset is high. In passive state (nRESET) I pull signal to GND with
130k resistor. Pushing a button connects signal to 3.3vcc with 10R in
series. Signal is filtered with 0.1uF capasitor. This circuit works well in
the absence of CPLD.
Click to expand...
Save money, board space and headaches while gaining reliability with a
reset supervisor chip:

http://www.maxim-ic.com/quick_view2.cfm/qv_pk/1195

BP
 
Lower the external pulldown to something around 20k and that'll do the trick.
 
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