Cox of timing problem?

S

Smith

Guest
Hi all.
I've encountered problem in developing a simple BCD number display.
Hope you all can tell me what wrong that I did.
In the system, I use a 4-bits counter which supply the 4-bits inputs to
the 7-segment decoder, expecting the equivalent value of the 4-bits
binary number in BCD to be displayed in the 7-segment.

In my simulation of the system, I found that the counter works well,
counting from 0000 to 1111 perfectly. However, the simulation result in
the 7-segment display included the binary number of 0000, 0001, 0010,
and 0011 only. And then it repeats again. The rest combination of the
4-bits number are fail to be decoded. According to the simulation
result, it also shows that the decoded 0001 binary number take more
time before it changes to the decoded result of the 0010.

Is that because of the timing of the system cause this problem? Below
is the coding for my 7-segment decoder module. Hope you all can help me
to figure out the problem. Thanks.
_____________________________________________________________
module seg7 (clock, bcd, number_segments);

input clock;
input [3:0] bcd;
output [6:0]number_segments;
reg [6:0]number_segments;
reg [3:0]count;


//from previous 4-bits counter module
always @(posedge clock)
begin
count [3:0] = bcd;
end

// Create segment outputs
always @(bcd)
begin
case(bcd)
0000 : number_segments <= 7'b1110111;
0001 : number_segments <= 7'b0100100;
0010 : number_segments <= 7'b1011101;
0011 : number_segments <= 7'b1101101;
0100 : number_segments <= 7'b0101110;
0101 : number_segments <= 7'b1101011;
0110 : number_segments <= 7'b1111011;
0111 : number_segments <= 7'b0100101;
1000 : number_segments <= 7'b1111111;
1001 : number_segments <= 7'b1101111;
1010 : number_segments <= 7'b0111111;
1011 : number_segments <= 7'b1111010;
1100 : number_segments <= 7'b1010011;
1101 : number_segments <= 7'b1111100;
1110 : number_segments <= 7'b1011011;
1111 : number_segments <= 7'b0011011;
endcase
end

endmodule
 
You're counter is not feeding the decoder. You're using the input directly instead.

i.e. you need always @(count) case(count) etc.

Smith wrote:
Hi all.
I've encountered problem in developing a simple BCD number display.
Hope you all can tell me what wrong that I did.
In the system, I use a 4-bits counter which supply the 4-bits inputs to
the 7-segment decoder, expecting the equivalent value of the 4-bits
binary number in BCD to be displayed in the 7-segment.

In my simulation of the system, I found that the counter works well,
counting from 0000 to 1111 perfectly. However, the simulation result in
the 7-segment display included the binary number of 0000, 0001, 0010,
and 0011 only. And then it repeats again. The rest combination of the
4-bits number are fail to be decoded. According to the simulation
result, it also shows that the decoded 0001 binary number take more
time before it changes to the decoded result of the 0010.

Is that because of the timing of the system cause this problem? Below
is the coding for my 7-segment decoder module. Hope you all can help me
to figure out the problem. Thanks.
_____________________________________________________________
module seg7 (clock, bcd, number_segments);

input clock;
input [3:0] bcd;
output [6:0]number_segments;
reg [6:0]number_segments;
reg [3:0]count;


//from previous 4-bits counter module
always @(posedge clock)
begin
count [3:0] = bcd;
end

// Create segment outputs
always @(bcd)
begin
case(bcd)
0000 : number_segments <= 7'b1110111;
0001 : number_segments <= 7'b0100100;
0010 : number_segments <= 7'b1011101;
0011 : number_segments <= 7'b1101101;
0100 : number_segments <= 7'b0101110;
0101 : number_segments <= 7'b1101011;
0110 : number_segments <= 7'b1111011;
0111 : number_segments <= 7'b0100101;
1000 : number_segments <= 7'b1111111;
1001 : number_segments <= 7'b1101111;
1010 : number_segments <= 7'b0111111;
1011 : number_segments <= 7'b1111010;
1100 : number_segments <= 7'b1010011;
1101 : number_segments <= 7'b1111100;
1110 : number_segments <= 7'b1011011;
1111 : number_segments <= 7'b0011011;
endcase
end

endmodule
Click to expand...
 
module seg7 (clock, bcd, number_segments);


input clock;
input [3:0] bcd;
output [6:0]number_segments;
reg [6:0]number_segments;

// Create segment outputs
always @(posedge clk,bcd)
begin
if(clk)
begin
case(bcd)
0000 : number_segments <= 7'b1110111;
0001 : number_segments <= 7'b0100100;
0010 : number_segments <= 7'b1011101;
0011 : number_segments <= 7'b1101101;
0100 : number_segments <= 7'b0101110;
0101 : number_segments <= 7'b1101011;
0110 : number_segments <= 7'b1111011;
0111 : number_segments <= 7'b0100101;
1000 : number_segments <= 7'b1111111;
1001 : number_segments <= 7'b1101111;
1010 : number_segments <= 7'b0111111;
1011 : number_segments <= 7'b1111010;
1100 : number_segments <= 7'b1010011;
1101 : number_segments <= 7'b1111100;
1110 : number_segments <= 7'b1011011;
1111 : number_segments <= 7'b0011011;
endcase
end
end


endmodule

nisheeth
 
I see a few coding practices problems that make debugging this problem
more difficult than it has to be. The most important one, is that it is
good practice to always specify a default case in a case statement.
You'll want to assign the output to x when you hit the default case.

Once you do that and try running your simulation again, you'll notice
that you are actually hitting that default case, even though at first
glance it appears you have specified all possible cases. That will help
you zero in the major bug here. For some additional clues, carefully
write down which input to the case statement gives which output, and
once you do that for all 16 cases, you should be able to figure out the
problem. If you need some more help, post your work here and I'll add
some more comments.

In addition to the main problem, there are some lessor issues that seem
confusing. You seem to be using non-blocking assignment <= where I
would expect blocking assignment = , and vice versa. I don't think it
actually triggers a bug in this case, but something to look out for.
You also define a register, but don't use the output of that register.
 
First, you should use "<=" in your clock block, and "=" in combination block.
Second, you did not use the count anywhere.
At last, you should add "4'b" before 0000, like "4'b0000", otherwise they are treated as decimal number

"Smith" <smith1874@yahoo.com> wrote in
news:1144415361.246010.101810@z34g2000cwc.googlegroups.com:

Hi all.
I've encountered problem in developing a simple BCD number display.
Hope you all can tell me what wrong that I did.
In the system, I use a 4-bits counter which supply the 4-bits inputs
to the 7-segment decoder, expecting the equivalent value of the 4-bits
binary number in BCD to be displayed in the 7-segment.

In my simulation of the system, I found that the counter works well,
counting from 0000 to 1111 perfectly. However, the simulation result
in the 7-segment display included the binary number of 0000, 0001,
0010, and 0011 only. And then it repeats again. The rest combination
of the 4-bits number are fail to be decoded. According to the
simulation result, it also shows that the decoded 0001 binary number
take more time before it changes to the decoded result of the 0010.

Is that because of the timing of the system cause this problem? Below
is the coding for my 7-segment decoder module. Hope you all can help
me to figure out the problem. Thanks.
_____________________________________________________________
module seg7 (clock, bcd, number_segments);

input clock;
input [3:0] bcd;
output [6:0]number_segments;
reg [6:0]number_segments;
reg [3:0]count;


//from previous 4-bits counter module
always @(posedge clock)
begin
count [3:0] = bcd;
end

// Create segment outputs
always @(bcd)
begin
case(bcd)
0000 : number_segments <= 7'b1110111;
0001 : number_segments <= 7'b0100100;
0010 : number_segments <= 7'b1011101;
0011 : number_segments <= 7'b1101101;
0100 : number_segments <= 7'b0101110;
0101 : number_segments <= 7'b1101011;
0110 : number_segments <= 7'b1111011;
0111 : number_segments <= 7'b0100101;
1000 : number_segments <= 7'b1111111;
1001 : number_segments <= 7'b1101111;
1010 : number_segments <= 7'b0111111;
1011 : number_segments <= 7'b1111010;
1100 : number_segments <= 7'b1010011;
1101 : number_segments <= 7'b1111100;
1110 : number_segments <= 7'b1011011;
1111 : number_segments <= 7'b0011011;
endcase
end

endmodule
Click to expand...
 
I'm not familiar with how you've used a comma in the sensitivity list for the always block here,
but I don't think 'bcd' should be included. You only want the outputs to change when the posedge
clk occurs.

nisheethg@gmail.com wrote:
module seg7 (clock, bcd, number_segments);


input clock;
input [3:0] bcd;
output [6:0]number_segments;
reg [6:0]number_segments;

// Create segment outputs
always @(posedge clk,bcd)
begin
if(clk)
begin
case(bcd)
0000 : number_segments <= 7'b1110111;
0001 : number_segments <= 7'b0100100;
0010 : number_segments <= 7'b1011101;
0011 : number_segments <= 7'b1101101;
0100 : number_segments <= 7'b0101110;
0101 : number_segments <= 7'b1101011;
0110 : number_segments <= 7'b1111011;
0111 : number_segments <= 7'b0100101;
1000 : number_segments <= 7'b1111111;
1001 : number_segments <= 7'b1101111;
1010 : number_segments <= 7'b0111111;
1011 : number_segments <= 7'b1111010;
1100 : number_segments <= 7'b1010011;
1101 : number_segments <= 7'b1111100;
1110 : number_segments <= 7'b1011011;
1111 : number_segments <= 7'b0011011;
endcase
end
end


endmodule

nisheeth
Click to expand...
 
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