Counting/comparing

I'm unable to get what I think is some simple code to work.

I'm loading a 16-bit register via SPI bus input as shown in Code
Section 1 below. Note NPCS corresponds to a 4-bit set of input pins
defining the selected channel, in this case `ZDAC. SPCK is the
incoming SPI clock.

After I attempt to load the count into ZDACCmd I try to compare it to
0x8000 (16'b1000000000000000) to determine if I should turn an ENable
ON in Code Section 2 below.

Begin code section 1: *********

reg [15:0] ZDACCmd = 16'b0;

wire ZSelect = !(NPCS==`ZDAC);
wire ZCmdClk = (NPCS==`ZDAC) ? SPCK : 1;

reg [4:0] ZCmdClkCount = 5'b0;

always @ ( posedge ZCmdClk or negedge ZSelect )
begin

if(!ZSelect)
begin
ZCmdClkCount = 0;
end
else
begin

case( ZCmdClkCount )
0:
begin
ZDACCmd <= 0;
end
8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23:
begin
ZDACCmd[23-ZCmdClkCount] <= MOSI;
end
endcase

ZCmdClkCount = ZCmdClkCount + 1'b1;

end

end

Begin code section 2 **********

if( Function==`WRBITBANK0 )
begin
case(Channel)
`ZENABLE:
begin

if((DATA[0]==`ENABLE_OUTPUT)&(ZDACCmd[15:0]>16'b1000000000000000))
ZEN <= `ENABLE_OUTPUT;
else
ZEN <= `DISABLE_OUTPUT;
end

End code *******

Is there anything obvious I'm doing wrong?

Thanks,

Chip Burns

 

[John_H]

chip@cruzio.com wrote:

I'm unable to get what I think is some simple code to work.

I'm loading a 16-bit register via SPI bus input as shown in Code
Section 1 below. Note NPCS corresponds to a 4-bit set of input pins
defining the selected channel, in this case `ZDAC. SPCK is the
incoming SPI clock.

After I attempt to load the count into ZDACCmd I try to compare it to
0x8000 (16'b1000000000000000) to determine if I should turn an ENable
ON in Code Section 2 below.

Begin code section 1: *********

reg [15:0] ZDACCmd = 16'b0;

wire ZSelect = !(NPCS==`ZDAC);
wire ZCmdClk = (NPCS==`ZDAC) ? SPCK : 1;

reg [4:0] ZCmdClkCount = 5'b0;

always @ ( posedge ZCmdClk or negedge ZSelect )
begin

if(!ZSelect)
begin
ZCmdClkCount = 0;
end
else
begin

case( ZCmdClkCount )
0:
begin
ZDACCmd <= 0;
end
8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23:
begin
ZDACCmd[23-ZCmdClkCount] <= MOSI;
end
endcase

ZCmdClkCount = ZCmdClkCount + 1'b1;

end

end

Begin code section 2 **********

if( Function==`WRBITBANK0 )
begin
case(Channel)
`ZENABLE:
begin

if((DATA[0]==`ENABLE_OUTPUT)&(ZDACCmd[15:0]>16'b1000000000000000))
ZEN <= `ENABLE_OUTPUT;
else
ZEN <= `DISABLE_OUTPUT;
end

End code *******

Is there anything obvious I'm doing wrong?

Thanks,

Chip Burns

First thing you're doing wrong - in my opinion - is using tabs. Stop
it! Tabs are never good. Stop it! Ahhhhh..... Okay:

Your logic on ZSelect and the gated clock result in the ZCmdClkCount
counter being reset when NPCS==`ZDAC which also happens to be the only
time you enable the clock. What do you want to happen here? Figure out
the reset and the clock gating and your logic will simulate.

------- A Caution --------

The gated clock may become your real problem.

The clock has a strong opportunity to get things confused. If ZCmdClk
isn't treated as a low-skew routing resource, the transition could get
to a register clock after the input data to that register has already
started changing. Your target architecture could determine how bad this
may (or may not) be for your design.


Alos, consider using the blocking operator (=) only for simulation where
you want to wait for something to update before proceeding. Most
synthesis-target Verilog code uses non-blocking operators (<=) such that
everything updates on one clock edge, just like the hardware should.
The synthesizers can handle blocking operators for those rare situations
where they're needed but never a mix of blocking and non-blocking
operators for the same register.

Consider something like:

always @(posedge SPCK or negedge ZSelect) // ungated clock
if( !ZSelect )
begin
ZCmdClkCount <= 0; // Was there a reason for the "="?
ZDACCmd <= 0; // If you figure out the enable
end // versus reset issue, this may help
else if( NPCS==`ZDAC ) // Clock enable allows SPCK to be low skew
begin
case( ZCmdClkCount )
0 : ZDACCmd <= 0;
8 ,9 ,10,11,
12,13,14,15,
16,17,18,19,
20,21,22,23: ZDACCmd[23-ZCmdClkCount] <= MOSI;
endcase
ZCmdClkCount <= ZCmdClkCount + 1'b1;
end