counter with different rates...

[Ahmad]

Hi,
I'm using Spartan3E FPGA from Xilinx, i want to use variable data rate
in my system (that means varaiable clock generation as i understood)..

Targeted rates (clocks) are varying from: 4.8kbps to 512kbps ... with
step of 1bps !!!

Questions:

1) Does that mean i have to have 4.8, 4.801, 4.802, ... 512 kbps
clocks?? i.e. 507.2k different clocks????

2) Assuming the answer of the above question is "YES", then i wan to
have a programmable clock generator block that generates the required
rates.. How can this be practically done on my FPGA??

3) Can the DCM available on my FPGA be used to generate such clocks??
how ??

Thank you for any kind of help or suggestion...
Best Regards,
Ahmad,

 

[Mike Treseler]

Ahmad wrote:

I'm using Spartan3E FPGA from Xilinx, i want to use variable data rate
in my system (that means varaiable clock generation as i understood)..

I would use one clock and generate variable clock enables.

1) Does that mean i have to have 4.8, 4.801, 4.802, ... 512 kbps
clocks?? i.e. 507.2k different clocks????

No.

2) Assuming the answer of the above question is "YES", then i wan to
have a programmable clock generator block that generates the required
rates.. How can this be practically done on my FPGA??

A prescaler like this:
http://home.comcast.net/~mike_treseler/count_enable.vhd

can handle for powers of two,
but for small changes like yours,
a phase accumulator is a better match.

3) Can the DCM available on my FPGA be used to generate such clocks??
how ??

DCMs and PLLs can be useful, but they
are also device specific and have
their own set of limitations for design,
start up, and timing.

-- Mike Treseler

 

[Ahmad]

I'm using Spartan3E FPGA from Xilinx, i want to use variable data rate
in my system (that means varaiable clock generation as i understood)..

I would use one clock and generate variable clock enables.

What do you mean? I think this will need large number of enables?

Sorry, i can't understand your point of view.

1) Does that mean i have to have 4.8, 4.801, 4.802, ... 512 kbps
clocks?? i.e. 507.2k different clocks????

No.

Then what? I got mad indeed trying to understand it!!

2) Assuming the answer of the above question is "YES", then i wan to
have a programmable clock generator block that generates the required
rates.. How can this be practically done on my FPGA??

A prescaler like this:http://home.comcast.net/~mike_treseler/count_enable.vhd

can handle for powers of two,
but for small changes like yours,
a phase accumulator is a better match.

I want to know more about phase accumulator.

3) Can the DCM available on my FPGA be used to generate such clocks??
how ??

DCMs and PLLs can be useful, but they
are also device specific and have
their own set of limitations for design,
start up, and timing.

I totally agree with you! I didn't think in that point before.

Really, thank you for your valuable replies...
Kind regards,
Ahmad,