Counter with carry out at embedded bit.

J

Jan Kindt

Guest
Sorry is the subject sounds confusing, was the best description I
could come up with...

Below is the code I have some questions about..
What I want is a 10bit counter (which acts as a write address to a
ram) with a signal indicating the following counter transitions :
31-->32
63-->64
95-->96
127-->128
and so forth for the rest of the 10bit values...
To do so, I've split up the counter in two halves as you can see in
the code.
Functionally, everything looks OK. The synthesiser makes two seperate
counters with the carry out of the first one, feeding the second. No
carry resource are used for that connection. But I'd like the
synthesiser (XST in my case) to use one long carry chain (one 10bit
counter) & make a connection at the right carry position to allow for
the signal. I took a closer look to the Virtex2pro slice architecture
& according to the datasheets, a connection like the one I want is
possible.

1. Can anyone give me any hints or so on how to code such a counter so
that the synthesis tool get my point in using one big counter ?
2. How could I make the whole thing parameterisable ? I have a
constant which indicates the cycle at wich the counter should output
the signal. Do I need to go for something like :
constant c_carryposition : natural = log(c_cycle)/log(2)


Thanks for any replies..

***************************
START CODE
***************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter_with_signalling is
Port (
clk : in std_logic;
Cnt_ena, Rst : in std_logic;
Count : out std_logic_vector(10 downto 0);
RdRq : out std_logic
);
end Counter_with_signalling;

architecture Behavioral of Counter_with_signalling is

signal countL : std_logic_vector(4 downto 0);
signal countL_async : std_logic_vector(5 downto 0);
signal countH_async, countH : std_logic_vector(5 downto 0);

begin

countL_async <= ('0' & countL) + 1;
countH_async <= countH + countL_async(5);

process (clk)
begin
if rising_edge(clk) then
if Rst = '1' then
countL <= (others => '0');
countH <= (others => '0');
else if Cnt_ena = '1' then
countL <= countL_async(4 downto 0);
countH <= countH + countL_async(5);
end if;
end if;
RdRq <= countL_async(5);
end if;
end process;

Count <= countH & countL;

end Behavioral;
 
Jan,
For synthesis, try the following minor tweeks:

-- Conditional incrementer
countL_async <= ('0' & countL) + Cnt_ena ; -- ok for std_logic_arith
-- countL_async <= ('0' & countL) + ("0" & Cnt_ena) ; -- for numeric_std

countH_async <= countH + countL_async(5);


process (clk)
begin
if rising_edge(clk) then
if Rst = '1' then
countL <= (others => '0');
countH <= (others => '0');
else
Click to expand...
countL <= countL_async(4 downto 0);
countH <= countH_async ;

end if;
end if;
RdRq <= countL_async(5);
end if;
end process;

Count <= countH & countL;
Click to expand...
For parameterization (where you have multiple designs with
different values), look at generics. You might also consider
altering your view point. Rather than 32 use 5. It is very
easy to go from there to 32 (2**5).

Cheers,
Jim Lewis
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Jan Kindt wrote:

Sorry is the subject sounds confusing, was the best description I
could come up with...

Below is the code I have some questions about..
What I want is a 10bit counter (which acts as a write address to a
ram) with a signal indicating the following counter transitions :
31-->32
63-->64
95-->96
127-->128
and so forth for the rest of the 10bit values...
To do so, I've split up the counter in two halves as you can see in
the code.
Functionally, everything looks OK. The synthesiser makes two seperate
counters with the carry out of the first one, feeding the second. No
carry resource are used for that connection. But I'd like the
synthesiser (XST in my case) to use one long carry chain (one 10bit
counter) & make a connection at the right carry position to allow for
the signal. I took a closer look to the Virtex2pro slice architecture
& according to the datasheets, a connection like the one I want is
possible.

1. Can anyone give me any hints or so on how to code such a counter so
that the synthesis tool get my point in using one big counter ?
2. How could I make the whole thing parameterisable ? I have a
constant which indicates the cycle at wich the counter should output
the signal. Do I need to go for something like :
constant c_carryposition : natural = log(c_cycle)/log(2)


Thanks for any replies..

***************************
START CODE
***************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter_with_signalling is
Port (
clk : in std_logic;
Cnt_ena, Rst : in std_logic;
Count : out std_logic_vector(10 downto 0);
RdRq : out std_logic
);
end Counter_with_signalling;

architecture Behavioral of Counter_with_signalling is

signal countL : std_logic_vector(4 downto 0);
signal countL_async : std_logic_vector(5 downto 0);
signal countH_async, countH : std_logic_vector(5 downto 0);

begin

countL_async <= ('0' & countL) + 1;
countH_async <= countH + countL_async(5);

process (clk)
begin
if rising_edge(clk) then
if Rst = '1' then
countL <= (others => '0');
countH <= (others => '0');
else if Cnt_ena = '1' then
countL <= countL_async(4 downto 0);
countH <= countH + countL_async(5);
end if;
end if;
RdRq <= countL_async(5);
end if;
end process;

Count <= countH & countL;

end Behavioral;
Click to expand...
 
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