Counter verifiaction with requirements

[JSreeniv]

Hi all

i am presently doing verification and validation of my module, and i
have these requirements for writing the testbenches and to simulate.
If possible could you please give me some cleared steps for combining
all these requirements. I am confuesd in making clear steps.

The count_pulses_for_period_pc0 is a register/counter that contains
the time period left to count the rising edges of the pulse_din0 pin
via Pulse Counter 0. This register is loadable and readable via the
processor. It will be referred to as CNT_P4P_PC0. The CNT_P4P_PC0 will
satisfy the following requirements.


1) The count_pulses_for_period_pc0 register shall be asserted to
0x0_0000 when the por_n signal is asserted low.

2) The count_pulses_for_period_pc0 register shall be asserted to
0x0_0000 when bit 20 of the inhibit1 register is written to a 1 and
the conditions in 1 are not met.

3) The CNT_P4P_PC0 shall be a processor loadable down counter with a
range of a minimum of 100 ns to a maximum of 1.3 s.

4) Reading of the contents of CNT_P4P_PC0 shall not corrupt any
measurement that is in progress.

5) The CNT_P4P_PC0 shall start and continue decrementing at a rate of
100ns when the pulse_cnt_config(3:2) are set to 00, 1us when the
pulse_cnt_config(3:2) are set to 01 or 10us when the pulse_cnt_config
(3:2) are set to 1x and the following sequence of conditions occur.

a) The pulse_cnt_config(1:0) = 11.
b) The CNT_P4P_PC0 does not equal 0x0_0000.
c) A 1 is written to the pulse_cnt_ctrl register bit 0
(Start measurement).

6) The CNT_P4P_PC0 shall stop decrementing when any of the following
conditions occur.
a) The CNT_P4P_PC0 equals 0x0_0000.
b) The pulse_cnt_config(1:0) does not equal 11.
c) The pulse_cnt_ctrl register bit 8 equals 0(PC 0 Reset).

7) The value in the CNT_P4P_PC0 shall not be affected by the state of
bit 8 in the pulse_cnt_ctrl register.

Please anyone give me the clear steps to verify the process.
waiting for your responses...please

Sreeni.J