Counter in FSM doesn't work

Hello ng,

I have a problem with my fsm.
I use a counter to count numbers of the pass through.

here my vhdl code (simple version):

process(i_rst_n,i_clk_fpt)
begin
if (i_rst_n= '0') then
state <= IDLE;
elsif rising_edge(i_clk_fpt) then -- risign edge
state <= nextstate;

end if;
end process;


process(state)
begin
case(state) is
when IDLE =>
cnt <= 0;
nextstate <= COUNT;
when COUNT =>
if (cnt < 8) then
cnt <= cnt +1;
else
cnt <= 0;
end if;
nextstate <= COUNT;

end case;

end process;

Now i get this warning:

Warning: Found 33 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
@W: BN134 :"d:\logik\counter\cnt.vhd":37:1:37:4|Found combinational
loop during mapping
1) instance o_count[31:0] work.cnt(behavioral)-o_count[31:0], output
net "o_count[0]" in work.cnt(behavioral)
input nets to instance: .........

 

[Frank Buss]

cpudesigner@gmx.at wrote:

process(state)
begin
case(state) is
when IDLE =
cnt <= 0;
nextstate <= COUNT;
when COUNT =
if (cnt < 8) then
cnt <= cnt +1;
else
cnt <= 0;
end if;
nextstate <= COUNT;

end case;

end process;

This is not clocked, so it counts all the time while state = COUNT, which
doesn't lead to a useful schematic.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

 

[Jyke]

<cpudesigner@gmx.at> wrote in message
news:1182852672.393000.317530@w5g2000hsg.googlegroups.com...

Hello ng,

I have a problem with my fsm.
I use a counter to count numbers of the pass through.

here my vhdl code (simple version):

process(i_rst_n,i_clk_fpt)
begin
if (i_rst_n= '0') then
state <= IDLE;
elsif rising_edge(i_clk_fpt) then -- risign edge
state <= nextstate;

end if;
end process;


process(state)
begin
case(state) is
when IDLE =
cnt <= 0;
nextstate <= COUNT;
when COUNT =
if (cnt < 8) then
cnt <= cnt +1;
else
cnt <= 0;
end if;
nextstate <= COUNT;

end case;

end process;

Now i get this warning:

Warning: Found 33 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
@W: BN134 :"d:\logik\counter\cnt.vhd":37:1:37:4|Found combinational
loop during mapping
1) instance o_count[31:0] work.cnt(behavioral)-o_count[31:0], output
net "o_count[0]" in work.cnt(behavioral)
input nets to instance: .........

Since cnt is not inside a clocked process, it is not a register. So when
state is COUNT you increase the cnt as fast as the simulator can do it (with
no clock involved). You should recode it so, that cnt is registered, you
probably want it to be increased only on clock egde.

Jyke.

 

[Jonathan Bromley]

On Tue, 26 Jun 2007 03:11:12 -0700, cpudesigner@gmx.at wrote:

Hello ng,

I have a problem with my fsm.

<rant>
The problem arises because you are (imperfectly) following
the advice of idiotic textbooks, instead of following the
advice of experienced members of this newsgroup.
</rant>

process(i_rst_n,i_clk_fpt)
begin
if (i_rst_n= '0') then
state <= IDLE;
elsif rising_edge(i_clk_fpt) then -- risign edge
state <= nextstate;
end if;
end process;

process(state)
begin
case(state) is
when IDLE =
cnt <= 0;
nextstate <= COUNT;
[and much more]

Your combinational process is trying to represent
a counter on "cnt", but I see no registers for "cnt"
anywhere. Hence the combinational loops.

Your combinational process is the process that...
* you don't need
* many people here quite correctly tell you not to use
* causes all the trouble
* is a PITA to write

However, let's take it at face value and see what we can do.
FIRST: This is a state machine. Consequently, in many
situations, the next state will be the same as the current
state. Therefore, it is a VERY good idea to start the
next-state combinational process with adefault assignment:

process(state)
begin
nextstate <= state; ----- DEFAULT ASSIGNMENT
case(state) is
when IDLE =
cnt <= 0;
nextstate <= COUNT;

Second, we need registers on "cnt". So you better put those in
the registered process, along with the state variable. This means
that you now need two count signals: the registered version, and
the next-state signal (just like your state variable). This is
getting silly, isn't it?

Wouldn't it all be SO much easier to use a single process for the
whole mess?

If you really insist on keeping your evil do-like-the-textbook-says
two-process state machine, then please separate out the counter into
another clocked process, and use the state machine to create control
outputs that cause the counter to reset, count, decrement, bit-flip
or whatever. Then you have done something that many good designers
like to do - you have separated control logic from datapath.

Alternatively, if you want to merge the control logic and datapath,
put the whole thing in a single clocked process so that you don't
have absurd unnecessary next-state signals cluttering your
architecture. There have been many, many discussions here about
how to do that.

Sorry to flame you for something that's not your fault. Your
problem is a perfect example of why the textbook/undergraduate
two-process coding style is a diabolical mess. Leave it behind
you, ignore your prof's criticisms, get on with doing the job
in a sensible way.

Grrrr.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[KJ]

"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message
news:irp183tvlhbbojsomlqtrsvn0i1dukul00@4ax.com...

Sorry to flame you for something that's not your fault. Your
problem is a perfect example of why the textbook/undergraduate
two-process coding style is a diabolical mess. Leave it behind
you, ignore your prof's criticisms, get on with doing the job
in a sensible way.

Grrrr.
--
Jonathan Bromley, Consultant

SOMEBODY is in a cranky mood today...chill out, relax

But I do agree with the technical aspects of your post.

KJ

 

[Jonathan Bromley]

On Tue, 26 Jun 2007 11:27:44 GMT, "KJ"
<kkjennings@sbcglobal.net> wrote:

Grrrr.

SOMEBODY is in a cranky mood today...chill out, relax

Sorry. Too much blood in the caffeine-stream, or something.
Anyway, at my age I'm allowed the occasional curmudgeonly
rant before Matron comes round with the tea and biscuits.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.