J
Jukka Marin
Guest
Dear All,
I'm learning Verilog (and FPGA's). At least I _hope_ I'm learning. ;-)
I'm using Altera Cyclone III in this project. I have a strange problem
which I haven't been able to solve. (I have a feeling that it might be
best to rewrite the Verilog code, but I can't to that right now.)
I have a real time counter which is clocked by clk:
reg [31:0] utime;
always @(posedge clk) begin
if (softreset) begin
utime = 0;
end else begin
utime = utime + 1;
end
end
The FPGA has an asynchronous bus to MCU which has no relation to the clock
feeding the counter above. The MCU can read the counter like this (code
simplified):
output reg [31:0] dout;
...
always @(negedge rd) begin
if (cs == 0) begin
dout = utime;
end
end
Most of the time, reading utime works just fine. However, sometimes the
value returned is invalid - it looks like utime was read while being
incremented and some of the bits had the old value, some had the new value.
Well, I thought this was natural because rd and clk are separate clocks,
so I changed the system to this:
reg [31:0] utime_bus, utime;
always @(posedge clk) begin
if (softreset) begin
utime = 0;
end else begin
utime = utime + 1;
end
end
always @(negedge clk) begin
// utime is stable, latch it to utime_bus
utime_bus = utime;
end
always @(negedge rd) begin
if (cs == 0) begin
dout = utime_bus;
end
end
The idea was to latch the counter value while it was stable and then pass
the latched value to MCU bus. Well, it didn't work any better (I guess
that might be because utime_bus can still be read while it is being updated).
The next attempt involved a flag, set by the MCU and used to disable utime_bus
updates before MCU read operation. Did not help, either.
We have checked the MCU bus timing (bus cycles should be long enough) and it
seems reading anything else (FPGA registers with static values) works just
fine. It's just the time counter that is causing problems.
I'm probably doing something fundamentally wrong here and I hope someone will
point out what it is and how to fix it
I know it would be better to have
one master clock to run all the logic, but we have 5 or 6 asynchronous clocks
feeding the FPGA.
While I'm at it, what is the correct way of creating a "set/reset flip-flop"
with independent set and reset clocks in Verilog? Like setting a flag when
MCU reads a register (using rd as clock) and resetting the flag when an
internal operation has been performed (using clk as clock)?
Thanks a lot!
-jm
I'm learning Verilog (and FPGA's). At least I _hope_ I'm learning. ;-)
I'm using Altera Cyclone III in this project. I have a strange problem
which I haven't been able to solve. (I have a feeling that it might be
best to rewrite the Verilog code, but I can't to that right now.)
I have a real time counter which is clocked by clk:
reg [31:0] utime;
always @(posedge clk) begin
if (softreset) begin
utime = 0;
end else begin
utime = utime + 1;
end
end
The FPGA has an asynchronous bus to MCU which has no relation to the clock
feeding the counter above. The MCU can read the counter like this (code
simplified):
output reg [31:0] dout;
...
always @(negedge rd) begin
if (cs == 0) begin
dout = utime;
end
end
Most of the time, reading utime works just fine. However, sometimes the
value returned is invalid - it looks like utime was read while being
incremented and some of the bits had the old value, some had the new value.
Well, I thought this was natural because rd and clk are separate clocks,
so I changed the system to this:
reg [31:0] utime_bus, utime;
always @(posedge clk) begin
if (softreset) begin
utime = 0;
end else begin
utime = utime + 1;
end
end
always @(negedge clk) begin
// utime is stable, latch it to utime_bus
utime_bus = utime;
end
always @(negedge rd) begin
if (cs == 0) begin
dout = utime_bus;
end
end
The idea was to latch the counter value while it was stable and then pass
the latched value to MCU bus. Well, it didn't work any better (I guess
that might be because utime_bus can still be read while it is being updated).
The next attempt involved a flag, set by the MCU and used to disable utime_bus
updates before MCU read operation. Did not help, either.
We have checked the MCU bus timing (bus cycles should be long enough) and it
seems reading anything else (FPGA registers with static values) works just
fine. It's just the time counter that is causing problems.
I'm probably doing something fundamentally wrong here and I hope someone will
point out what it is and how to fix it
I know it would be better to haveone master clock to run all the logic, but we have 5 or 6 asynchronous clocks
feeding the FPGA.
While I'm at it, what is the correct way of creating a "set/reset flip-flop"
with independent set and reset clocks in Verilog? Like setting a flag when
MCU reads a register (using rd as clock) and resetting the flag when an
internal operation has been performed (using clk as clock)?
Thanks a lot!
-jm