Count with specific bits of the counter

Hi all,

I am trying to create a counter of say 10 bits, where only some of
these bits are used in counting. These bits will be indicated by a
second 10bit signal.

So for example if that 10-bit control signal is 0000110011 then the
count would be

0000000000
0000000001
0000000010
0000000011
0000010000
0000010001
0000010010
.
.
.
0000110011

My idea is a single bit ripple carry adder structure where multiplexers
are used to by-pass specific adders so that the carry is only fed to
the right ones. I am looking for a more elegant VHDL-style description.
I'd appreciate the help.

 

Well since i didnt get any replies I did it the long way. I'm
posting it here for future reference

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

--counter with bit selection, counts using only the bits
--specified in the input sel signal

entity cntr_bit_select is
Generic ( NUM_OF_NODES : integer := 10);
Port ( clk : in std_logic;
reset : in std_logic;
en : in std_logic;
sel : in std_logic_vector(NUM_OF_NODES - 1 downto 0);
cnt : out std_logic_vector(NUM_OF_NODES - 1 downto 0));

end cntr_bit_select;

architecture Behavioral of cntr_bit_select is

--declare multiplexer outputs
signal mux_out : std_logic_vector(NUM_OF_NODES - 1 downto 0);

--declare sum_out, carry_out and register signals
signal sum_out : std_logic_vector(NUM_OF_NODES - 1 downto 0);
signal carry_out : std_logic_vector(NUM_OF_NODES - 1 downto 0);
signal reg_out : std_logic_vector(NUM_OF_NODES - 1 downto 0);

begin

--create the multiplexers
mux : process(mux_out, carry_out, sel)
begin
for i in NUM_OF_NODES - 1 downto 1 loop
--for the N-1 MSB's select between the previous MUX output and
--the carry out bit of the HA
if sel(i) = '0' then
mux_out(i) <= mux_out(i - 1);
else
mux_out(i) <= carry_out(i);
end if;
end loop;

--for the LSB select between a '1' and the carry out bit
if sel(0) = '0' then
mux_out(0) <= '1';
else
mux_out(0) <= carry_out(0);
end if;
end process mux;

--create the half adders
ha : process(reg_out, mux_out)
begin
--for the N-1 MSB's add the output of the previous MUX
--with the corresponding bit from the register
for i in NUM_OF_NODES - 1 downto 1 loop
sum_out(i) <= reg_out(i) XOR mux_out(i - 1);
carry_out(i) <= reg_out(i) AND mux_out(i - 1);
end loop;

--for the LSB add '1' to the corresponding bit from
--the register
sum_out(0) <= NOT reg_out(0);
carry_out(0) <= reg_out(0);
end process ha;

--create the registers
reg : process
begin

wait until clk'event and clk='1';

if en = '1' then
for i in NUM_OF_NODES - 1 downto 0 loop
if sel(i) = '1' then
reg_out(i) <= sum_out(i);
end if;
end loop;
end if;

if reset = '1' then
reg_out <= (others=>'0');
end if;

end process reg;

--assign count to output bus
cnt <= reg_out;

end Behavioral;

 

[Weng Tianxiang]

Hi,
You should go in a reverse way.

That is:
1. Do a normal counter;
2. Use another std_logic_vector(10 downto 0) to map the pins relation
as you want.

Logic would become much easier.

Weng

skatoulas@hotmail.com wrote:

Well since i didnt get any replies I did it the long way. I'm
posting it here for future reference

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

--counter with bit selection, counts using only the bits
--specified in the input sel signal

entity cntr_bit_select is
Generic ( NUM_OF_NODES : integer := 10);
Port ( clk : in std_logic;
reset : in std_logic;
en : in std_logic;
sel : in std_logic_vector(NUM_OF_NODES - 1 downto 0);
cnt : out std_logic_vector(NUM_OF_NODES - 1 downto 0));

end cntr_bit_select;

architecture Behavioral of cntr_bit_select is

--declare multiplexer outputs
signal mux_out : std_logic_vector(NUM_OF_NODES - 1 downto 0);

--declare sum_out, carry_out and register signals
signal sum_out : std_logic_vector(NUM_OF_NODES - 1 downto 0);
signal carry_out : std_logic_vector(NUM_OF_NODES - 1 downto 0);
signal reg_out : std_logic_vector(NUM_OF_NODES - 1 downto 0);

begin

--create the multiplexers
mux : process(mux_out, carry_out, sel)
begin
for i in NUM_OF_NODES - 1 downto 1 loop
--for the N-1 MSB's select between the previous MUX output and
--the carry out bit of the HA
if sel(i) = '0' then
mux_out(i) <= mux_out(i - 1);
else
mux_out(i) <= carry_out(i);
end if;
end loop;

--for the LSB select between a '1' and the carry out bit
if sel(0) = '0' then
mux_out(0) <= '1';
else
mux_out(0) <= carry_out(0);
end if;
end process mux;

--create the half adders
ha : process(reg_out, mux_out)
begin
--for the N-1 MSB's add the output of the previous MUX
--with the corresponding bit from the register
for i in NUM_OF_NODES - 1 downto 1 loop
sum_out(i) <= reg_out(i) XOR mux_out(i - 1);
carry_out(i) <= reg_out(i) AND mux_out(i - 1);
end loop;

--for the LSB add '1' to the corresponding bit from
--the register
sum_out(0) <= NOT reg_out(0);
carry_out(0) <= reg_out(0);
end process ha;

--create the registers
reg : process
begin

wait until clk'event and clk='1';

if en = '1' then
for i in NUM_OF_NODES - 1 downto 0 loop
if sel(i) = '1' then
reg_out(i) <= sum_out(i);
end if;
end loop;
end if;

if reset = '1' then
reg_out <= (others=>'0');
end if;

end process reg;

--assign count to output bus
cnt <= reg_out;

end Behavioral;