Could you explain the assign usage in this example?

Hi,
I got a short verilog tutorial on line.

I feel that I understand the last part after "and any variable that is..." of the
below paragraph.

But it looks like for me that it does not explain the error of the example.

.. Is it (assign LP=3'b101 a continuous assignment?

For me, (assign LP=3'b101 is just what "Any variable that is continuously
assigned (using assign keyword) has to be wire" requires.

Could you explain it to me?


Thanks,



Q: Is the following code fragment correct?

wire[2:0] LP;
initial begin
assign LP=3'b101;
end

Wrong. Any variable that is continuously assigned (using assign keyword) has to
be wire, and any variable that is assigned using = inside an always or initial
block has to be of type reg.

 

[GaborSzakacs]

rxjwg98@gmail.com wrote:

Hi,
I got a short verilog tutorial on line.

I feel that I understand the last part after "and any variable that is..." of the
below paragraph.

But it looks like for me that it does not explain the error of the example.

. Is it (assign LP=3'b101 a continuous assignment?

For me, (assign LP=3'b101 is just what "Any variable that is continuously
assigned (using assign keyword) has to be wire" requires.

Could you explain it to me?


Thanks,



Q: Is the following code fragment correct?

wire[2:0] LP;
initial begin
assign LP=3'b101;
end

Wrong. Any variable that is continuously assigned (using assign keyword) has to
be wire, and any variable that is assigned using = inside an always or initial
block has to be of type reg.

In the example, the assign is inside an initial block, making it a
"procedural continuous assignment." So in this case LP should be
a reg rather than a wire. If there is no other block that has
a deassign for LP, it would have the same effect as a "continuous
assignment," since it starts at the beginning of simulation. This
form of assignment is an advanced concept, and not generally
synthesizable.

--
Gabor