R
ram
Guest
I am prototyping a IP core which was written in verilog languge in
cyclone II FPGA.My application engineer wrote code in C for
application level.Can i simulate the both in cadence simulation
environment so that i can find the bug in real environment .Can anyone
suggest on this.I am in desperate situation.Please help me.
Thanking you kumar
cyclone II FPGA.My application engineer wrote code in C for
application level.Can i simulate the both in cadence simulation
environment so that i can find the bug in real environment .Can anyone
suggest on this.I am in desperate situation.Please help me.
Thanking you kumar