correct way to implement muxing of signals

[googler]

Hi all,

I have a question on how to design a piece of logic the right way.
This is not exactly a question on the Verilog language per se,
although I am in fact implementing it in Verilog.

I have three different clock domains. Each of these clock domains are
for different speed of data transfer and each of them has similar set
of signals. For each clock domain, we have the clock, reset bar, speed
select and a data valid signal. Say the different speeds are A, B and
C. So for speed A, we have the following signals:
clk_A, rstn_A, spdsel_A, dvalid_A

There are similar set of signals for speeds B and C. Only one of the
signals spdsel_A, spdsel_B and spdsel_C can be asserted at a given
time. Also, speed change does not happen frequently, so the spdsel_A,
spdsel_B and spdsel_C signals can probably be thought of as static.

The logic I want to design is basically a counter to count the number
of data valid signals for whatever speed is currently being used.
However, I just want to use one counter instead of using three
different counters for the three speeds (to save on area and power)
and I want to have only one clk, rstn and data_valid signal going to
this counter, chosen based on which spdsel line is active. I want to
know what is the right way to select the clock, reset bar and data
valid signals. This is what I have currently, probably the simplest
way to do this, but not sure if this is 100% correct. I also have some
doubt that this might be a bit difficult for synthesis/timing
analysis.

assign data_valid = spdsel_A? dvalid_A :
spdsel_B? dvalid_B :
spdsel_C? dvalid_C :
1'b0;

assign clk = spdsel_A? clk_A :
spdsel_B? clk_B :
spdsel_C? clk_C :
1'b0;

assign rstn = spdsel_A? rstn_A :
spdsel_B? rstn_B :
spdsel_C? rstn_C :
1'b0;

Please comment about the correctness of the above implementation and
suggest if there are better ways to do the same.

Thanks!

 

[glen herrmannsfeldt]

googler <pinaki_m77@yahoo.com> wrote:

I have a question on how to design a piece of logic the right way.
This is not exactly a question on the Verilog language per se,
although I am in fact implementing it in Verilog.

I have three different clock domains. Each of these clock domains are
for different speed of data transfer and each of them has similar set
of signals. For each clock domain, we have the clock, reset bar, speed
select and a data valid signal. Say the different speeds are A, B and
C. So for speed A, we have the following signals:
clk_A, rstn_A, spdsel_A, dvalid_A

The usual meaning of the term 'clock domain' is for a circuit
that has some parts clocked by one clock, and others clocked by a
different clock, all running at the same time.

Multiple clocks with a clock multiplexer is a different problem.
I believe that there is a way to switch clocks while avoiding
the 'short clock cycle' that can happen during such a switch.
I haven't actually thought about that recently, and don't
remember how it works. Though it isn't so obvious that
your design has that problem.

-- glen

 

[gabor]

On Sunday, February 20, 2011 8:39:52 PM UTC-5, googler wrote:

Hi all,

I have a question on how to design a piece of logic the right way.
This is not exactly a question on the Verilog language per se,
although I am in fact implementing it in Verilog.

I have three different clock domains. Each of these clock domains are
for different speed of data transfer and each of them has similar set
of signals. For each clock domain, we have the clock, reset bar, speed
select and a data valid signal. Say the different speeds are A, B and
C. So for speed A, we have the following signals:
clk_A, rstn_A, spdsel_A, dvalid_A

There are similar set of signals for speeds B and C. Only one of the
signals spdsel_A, spdsel_B and spdsel_C can be asserted at a given
time. Also, speed change does not happen frequently, so the spdsel_A,
spdsel_B and spdsel_C signals can probably be thought of as static.

The logic I want to design is basically a counter to count the number
of data valid signals for whatever speed is currently being used.
However, I just want to use one counter instead of using three
different counters for the three speeds (to save on area and power)
and I want to have only one clk, rstn and data_valid signal going to
this counter, chosen based on which spdsel line is active. I want to
know what is the right way to select the clock, reset bar and data
valid signals. This is what I have currently, probably the simplest
way to do this, but not sure if this is 100% correct. I also have some
doubt that this might be a bit difficult for synthesis/timing
analysis.

assign data_valid = spdsel_A? dvalid_A :
spdsel_B? dvalid_B :
spdsel_C? dvalid_C :
1'b0;

assign clk = spdsel_A? clk_A :
spdsel_B? clk_B :
spdsel_C? clk_C :
1'b0;

assign rstn = spdsel_A? rstn_A :
spdsel_B? rstn_B :
spdsel_C? rstn_C :
1'b0;

Please comment about the correctness of the above implementation and
suggest if there are better ways to do the same.

Thanks!

If you don't need the count to be correct until you have
received a reset signal from the selected source, then
there's probably nothing wrong with this. You'll need
to make sure that the clock mux and data muxes don't
have enough difference in prop delay to cause setup
and hold issues at the counter.

Normally if I were multiplexing a rising-edge clock,
I would make the "off" state 1 rather than 0. Then
you could assure a glitch-free transition by making
each source select synchronous to the rising edge of
its own clock, and adding some logic that doesn't
assert a new clock source unless the other sources
are de-asserted. so in effect the last rising edge
of the currently select clock would shut off that
source select, which takes you into the "no select"
state with the clock remaining high. Then the
next source in line waits for its next rising
edge to enable its source select (clock is still
high) and finally the clock goes low at the next
falling edge of the second source. But as Glen
noted, you probably don't need this if you're
only running a counter and reset it on a regular
basis.

-- Gabor