Correct use of HDL

[Taha]

Dear all,

Can someone help me rewrite the segment of code below in order to make
the code read like a real HDL segment as opposed to a netlist whilst
still being able to compile into a maximum of 34 muxes per partial
product row. (i.e. I really dont belive that I should have to write out
the equation for each bit when I use an HDL, or else, whats the
advantage of HDL over schematic capture )

In addition, since I will need 8 rows of partial products, do i have to
create 8 instances of ppRow or can I use a for loop to put the data
into some sort of a matrix.

Please do note that this should be combinational logic only ... no
clocks/sequential ...

One more thing, if someone can be kind enough to send me a short
tutorial on how to use the Cadence IC tools (i.e. NC-Verilog, Encounter
RTL compiler, Virtuoso Schematic, Analog artist, Virtuoso Layout) to go
through a top - down design, i would really be grateful.

Sincerely,

Taha Amiralli


/**
* Partial Product Row
* Input: a - 16 bit Multiplicand
* sign - 1 bit from MBE
* shift - 1 bit from MBE
* pass - 1 bit from MBE
* Output: ppRow - 16 bit Partial product row given the sign, shift and
pass bits form the MBE stage
*/
module ppRow(a, sign, shift, pass, ppRow);

/* Inputs */
input [15:0]a;
input sign, shift, pass;

/* Outputs */
output [15:0]ppRow;

/* Datatypes */
integer i;
wire tmp;

/* RTL */
/// Partial Product row generation
assign ppRow[15] = (pass) ? ((sign)?a[15]:~a[15]) :
((sign)?a[15-1]:~a[15-1]);
assign ppRow[14] = (pass) ? ((sign)?a[14]:~a[14]) :
((sign)?a[14-1]:~a[14-1]);
assign ppRow[13] = (pass) ? ((sign)?a[13]:~a[13]) :
((sign)?a[13-1]:~a[13-1]);
assign ppRow[12] = (pass) ? ((sign)?a[12]:~a[12]) :
((sign)?a[12-1]:~a[12-1]);
assign ppRow[11] = (pass) ? ((sign)?a[11]:~a[11]) :
((sign)?a[11-1]:~a[11-1]);
assign ppRow[10] = (pass) ? ((sign)?a[10]:~a[10]) :
((sign)?a[10-1]:~a[10-1]);
assign ppRow[9] = (pass) ? ((sign)?a[9]:~a[9]) :
((sign)?a[9-1]:~a[9-1]);
assign ppRow[8] = (pass) ? ((sign)?a[8]:~a[8]) :
((sign)?a[8-1]:~a[8-1]);
assign ppRow[7] = (pass) ? ((sign)?a[7]:~a[7]) :
((sign)?a[7-1]:~a[7-1]);
assign ppRow[6] = (pass) ? ((sign)?a[6]:~a[6]) :
((sign)?a[6-1]:~a[6-1]);
assign ppRow[5] = (pass) ? ((sign)?a[5]:~a[5]) :
((sign)?a[5-1]:~a[5-1]);
assign ppRow[4] = (pass) ? ((sign)?a[4]:~a[4]) :
((sign)?a[4-1]:~a[4-1]);
assign ppRow[3] = (pass) ? ((sign)?a[3]:~a[3]) :
((sign)?a[3-1]:~a[3-1]);
assign ppRow[2] = (pass) ? ((sign)?a[2]:~a[2]) :
((sign)?a[2-1]:~a[2-1]);
assign ppRow[1] = (pass) ? ((sign)?a[1]:~a[1]) :
((sign)?a[1-1]:~a[1-1]);
assign ppRow[0] = (pass) ? ((sign)?a[0]:~a[0]) : 1'b0;

endmodule

 

[chainastole]

1)Transformation of your code to less strings is quite simple (under
asumption that it is correct):
ppRow[15:0] = (pass)? ((sign)? a[15:0]:~a[15:0]) :
((sign)?{a[14:0],1'b0}:{~a[14:0],1'b0});

2) You may produce 8 instances of the circuitry if your design
methodology allows you to use Verilog 2001, which allows multiple
instances automatic generation under compilation with the help of the
"generate" operator. See comprehensive guide at
http://www.sutherland-hdl.com/Verilog-2001.

 

[Taha]

Hello,

Thanks for the prompt reply....

I am trying out the code segment that you had proposed and I am getting
a syntax error (See below) at that line...

In fact, i had tried to initially do this as a for loop and got a
similar error... and i am not sure why!

Thanks,


D:\tmp>iverilog -o ppg.out ppg.v
ppg.v:133: parse error
ppg.v:133: error: Invalid module instantiation
Command signaled: C:\iverilog\lib\ivl\ivlpp -L -D__ICARUS__=1
-fd:\DOCUME~1\Tah
a\LOCALS~1\Temp\ivrlg2cbf | C:\iverilog\lib\ivl\ivl
-Cd:\DOCUME~1\Taha\LOCALS~1
\Temp\ivrlh2cbf -CC:\iverilog\lib\ivl\vvp.conf -- -

D:\tmp>

 

[Taha]

Hello again...

chainastole, your line seems to work in modelsim and I cant explain
why... It must be something wrong that I am doing .... In any case,
what if I had the following segment of code, how would I write it using
proper and synthesizable HDL...

(Mk, i tried the for loop again and it did not seem to work... compiler
error )

I addition, if i were to use the constants that were declared above the
code segment (eg input [MULTIPLIER_WIDTH-1:0]x; i also get a syntax
error)

Looks like my C/C++ background is not helping with my transition from
VHDL to verilog ....

Thanks a lot,

Taha

/* Constants */
`define MULTIPLIER_WIDTH 16
`define NUM_PP 8

/**
* Modified Booth Encoding
*
* Input: x - 16 bit multiplier
* Output: sign - 8 bits - Sign
* shift - 8 bit - Generate 2a
* pass - 8 bit - Generate a
*/
module mbe_16(x, sign, shift, pass);

/* Inputs */
input [15:0]x;

/* Outputs */
output [7:0]sign;
output [7:0]shift;
output [7:0]pass;

/* Datatypes */

/* RTL */
/// Modified Booth Encoding
assign sign [7] = x[15];
assign shift[7] = x[15] ^ x[15-1];
assign pass [7] = x[15-1] ^ x[15-2];

assign sign [6] = x[13];
assign shift[6] = x[13] ^ x[13-1];
assign pass [6] = x[13-1] ^ x[13-2];

assign sign [5] = x[11];
assign shift[5] = x[11] ^ x[11-1];
assign pass [5] = x[11-1] ^ x[11-2];

assign sign [4] = x[9];
assign shift[4] = x[9] ^ x[9-1];
assign pass [4] = x[9-1] ^ x[9-2];

assign sign [3] = x[7];
assign shift[3] = x[7] ^ x[7-1];
assign pass [3] = x[7-1] ^ x[7-2];

assign sign [2] = x[5];
assign shift[2] = x[5] ^ x[5-1];
assign pass [2] = x[5-1] ^ x[5-2];

assign sign [1] = x[3];
assign shift[1] = x[3] ^ x[3-1];
assign pass [1] = x[3-1] ^ x[3-2];

assign sign [0] = x[1];
assign shift[0] = x[1] ^ x[1-1];
assign pass [0] = x[1-1] ^ 0;

endmodule // mbe_16

 

[Taha]

Just to clarify, chainastole.... With respect to the use of 8 instances
of pprow, I would end up having a module with 8 outputs correct?

ie. module ppGen (instantiates 8 pprows) and returns the results of
each

module ppGen (multiplier, multiplicand, ppRow0, ppRow1, ppRow2, ppRow3
.... pprow7);
....
endmodule

is this what you had suggested?

Thanks once again.

taha

 

[chainastole]

Taha,
1) Specify, please, what is the problem with the use of the parameters.
2) Your mbe_16 code looks quite well. May be there is a way to express
it in more generous form with the help of any loop, but this form is,
indeed, synthesizable and readable. Just insert calculation results in
the ranges specification instead of the calculation formulas.
3) As for 8 instantiations question I don't think that I understand,
what is the problem. In the same way you produce multiple
instantiations of the modules in the higher hierarchy module, you may
generate multiple logic circuitries with the help of for loop and
generate operator in Verilog 2001. Written once it will produce indexed
instantiations of the specified logic, the output of which may, indeed,
be used for the internal calculations or be output to the higher
hierarchy.
4) The error, depicted by you:
ppg.v:133: error: Invalid module instantiation
Specify once more, please, when do you receive it, at what file run?

 

[Taha]

Hello again,

I do apologize for being late in responding...

1.) the only problem I had with the use of parameters is that
parameters are related to a module (or so i think) and hence if I
wanted a global constant, then that parameter will have to be declared
in every module that uses it... I found out that to use a macro you
need the BackStroke (`) and not the Regular stroke (') .... i.e. Syntax
error on my part Sorry.

3.) The only concern with having that many lines is that now, the
Verilog starts to look like a netlist. Thus, if I ever need to expand
my multiplier width, I am cutting and pasting as opposed to changing
constants.
The generate keyword worked just fine and hence I'll use that one
....thanks..

4.) that was the error that I used to get when using a for loop.... I
have switched compilers and i no longer get that error... and I did not
bother to figure out why

Thanks a lot ....

Sincerely,

Taha