Cordic-based Sine Computer in MyHDL

[Jan Decaluwe]

Hi:

I have added a page about a Cordic-based Sine Computer to
the MyHDL CookBook:

http://myhdl.jandecaluwe.com/doku.php/cookbook:sinecomp

This page demonstrates several features of the MyHDL to Verilog
convertor tool. In particular:

- it shows how the convertor takes care of the tricky issues
with negative numbers in Verilog automatically
- it shows how you can use non-synthesizable constructs in MyHDL
and still get synthesizable Verilog out of it (Really!)

Regards,

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com

 

[Kolja Sulimma]

Jan Decaluwe schrieb:

- it shows how you can use non-synthesizable constructs in MyHDL
and still get synthesizable Verilog out of it (Really!)

I heard a research talk on a GI workshop that talked about using simple
XSLT translations to make common unsynthesizable VHDL code synthesizable.

IMHO it is embarrassing that a 2006 compiler cannot synthesize

if rising_edge(clk) and enable='1' then...

Kolja Sulimma

 

[Mike Treseler]

Jan Decaluwe wrote:

I have added a page about a Cordic-based Sine Computer to
the MyHDL CookBook:

http://myhdl.jandecaluwe.com/doku.php/cookbook:sinecomp

Wow. A non-trivial example that works.
Beautiful generated code.
(Ignore the synthesis warnings, I think Jan has it right.)
You may be on to something.

Here's how Quartus sees it:
http://home.comcast.net/~mike_treseler/sinecomputer.pdf
_______________________
Top-level Entity Name : SineComputer
Family : Stratix II
Device : EP2S15F484C3
Timing Models : Final
Total ALUTs : 276 / 12,480 ( 2 % )
Total registers : 107
[vs. 131 in the example -- apples to oranges ]
Actual Time : 141.42 MHz ( period = 7.071 ns )
[ vs 87.385MHz in the example -- apples to oranges ]


-- Mike Treseler

 

[Jan Decaluwe]

Mike Treseler wrote:

Jan Decaluwe wrote:

I have added a page about a Cordic-based Sine Computer to
the MyHDL CookBook:

http://myhdl.jandecaluwe.com/doku.php/cookbook:sinecomp


Wow. A non-trivial example that works.
Beautiful generated code.
(Ignore the synthesis warnings, I think Jan has it right.)

Does Quartus issue warnings also?

No doubt the warnings are related to the use of blocking
assignments in a clocked always block. You know

At least XST doesn't declare this an error. My worst nightmare
would be that half-baked synthesis tools or Verilog gurus
would prevent me from writing code like this. It's a realistic
possibility that explains my occasional angry outbursts.

What I think happens is that XST creates a FF for any reg
in the code. When it detects that the Q output is not used,
it issues a warning. Fine with me, as long as it uses
the D input wire properly

An interesting side effect is that no warnings are issued
in the more "advanced" case when a reg is potentially
used immediately but also stored for later usage,
like the 'counting' flag in this example:

http://myhdl.jandecaluwe.com/doku.php/cookbook:stopwatch

Best regards,

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com

 

[Mike Treseler]

Jan Decaluwe wrote:

Does Quartus issue warnings also?
No doubt the warnings are related to the use of blocking
assignments in a clocked always block. You know

Yes, and the warning isn't even apropos in this case since
you've gone belt-and-suspenders with a single named block
and local declarations for every reg appearing left of an '='.
I will check if I there is some way to stifle the warning.

At least XST doesn't declare this an error.

I knew XST had to be better at something

My worst nightmare
would be that half-baked synthesis tools or Verilog gurus
would prevent me from writing code like this. It's a realistic
possibility that explains my occasional angry outbursts.

The tools have always allowed it,
and I suspect that a silent majority
of serious designers have used the
style without making a big deal of it.
There will always be quiet producers
and noisy lint-pickers.

What I think happens is that XST creates a FF for any reg
in the code. When it detects that the Q output is not used,
it issues a warning. Fine with me, as long as it uses
the D input wire properly

Synthesis really has to do this anyway
because wasting flops is a mortal sin.

An interesting side effect is that no warnings are issued
in the more "advanced" case when a reg is potentially
used immediately but also stored for later usage,
like the 'counting' flag in this example:

http://myhdl.jandecaluwe.com/doku.php/cookbook:stopwatch

Yes, synthesis is very clever.
Every variable-reg update gets
its own little "instance" of gates.

Keep up the good work and
don't let the b^st^rds get you down.
If I have to learn a new trick,
I think I would prefer python to systemverilog.

-- Mike Treseler

 

you can add also:

CORDIC Bibliography Site :
http://web.archive.org/web/20001017173921/http://devil.ece.utexas.edu/