V
~~ VerilogMan ~~
Guest
Hi ,
I have been spending a LOT of times creating this convoultion encoder...
When I try to run the testbecnh (the file named viertib_tb) my data in does
not match my data out for some odd reason... I think it comes from the add
compare select module ... but i did not manage to track it and find it ...
the design is composed of a encoder part and decoder part. encoder i am
pretty sure it works fine. It bugs somewhere in the dencoder files i think.
It could be also the modrwcounter file, the module sending the enables
signals.
Anyone could take a quick look at the files to see where the problem could
be from plz ?
Files are located at www.engsoc.org/~sorouche/code.zip
thx
I have been spending a LOT of times creating this convoultion encoder...
When I try to run the testbecnh (the file named viertib_tb) my data in does
not match my data out for some odd reason... I think it comes from the add
compare select module ... but i did not manage to track it and find it ...
the design is composed of a encoder part and decoder part. encoder i am
pretty sure it works fine. It bugs somewhere in the dencoder files i think.
It could be also the modrwcounter file, the module sending the enables
signals.
Anyone could take a quick look at the files to see where the problem could
be from plz ?
Files are located at www.engsoc.org/~sorouche/code.zip
thx
