Converting Verilog Test Env. to System Verilog & Open Vera

Hi All,

I am working on a Task of Converting Old BFMs and Test Environment
created in Verilog to System verilog and Open Vera.

That includes converting test benches and BFMs
Generating synopsys and user defined classes and making a high level
wrapper of system verilog to be used with Vera.

Please help me with guideline, documents and tips related to this task

Regards
Thanks in Advance

Kedar

 

[cliffc]

Hi, Kedar -

You may or may not already know this, but for other readers monitoring
this thread let me state what is already common knowledge:

SystemVerilog is fully backward compatible with Verilog-2001 and it
typically does not make sense to spend time converting old Verilog-2001
BFM testbenches to the new Synopsys class-based VMM-style of testbench.

For new testbenches, an approach like this does indeed make sense.

You first need to understand SystemVerilog syntax, and then you can
pursue this course of action by reading Janick Bergeron, et al's book,
Verification Methodology Manual for SystemVerilog, published by
Springer (new book).

You could hire some SystemVerilog consultants to help you do the work
(I don't do this myself).

You may also want to consider SystemVerilog for Verification training
to get started with this (I do do this

Regards - Cliff Cummings
Verilog & SystemVerilog Guru
www.sunburst-design.com

 

[Naren]

You could hire some SystemVerilog consultants to help you do the work
(I don't do this myself).

If you are in INDIA, www.toomuchsemi.com provides systemverilog
consultants...

Thanks & Regards,
Naren.

 

[Ajeetha]

Cliff,
Can you please elaborate why you say:

SystemVerilog is fully backward compatible with Verilog-2001 and it
typically does not make sense to spend time converting old Verilog-2001
BFM testbenches to the new Synopsys class-based VMM-style of testbench.

I see a lot of value in moving from traditional Verilog based TBs to a
SV/VMM based one - such as:

1. Opens possibility of constrained random verification
2. Better organized Verif. env in general

Though one may argue that VMM is not the only way, but it is certainly
ONE way and a good way too!

Specifically the OP said:

Generating synopsys and user defined classes and making a high level
wrapper of system verilog to be used with Vera.

By that hopefully he meant re-use exisitng BFM code and wrapping them
in VMM etc. - I would say that's THE way to go!

Kedar - contact ajeetha <AT> gmail.com if you want to outsource such
activity.

Regards
Ajeetha
www.noveldv.com

 

[raul]

It is possible to do constrained random verification using only Verilog
2001.

RAUL

 

[Muks]

no!
Not available in verilog-2k

Constrained random verification is introduced in System Verilog only.

$Muks

 

[raul]

Wrong!

I started doing constrained random verification using verilog and C in
1996. Constrained random verification is not language-related is how
you "constrain" "random" inputs to a Design-under-test to reach all
lines, conditions, branches, states (and arches) and toggle all bits
within an implementation of a functional specification.

If you are focused on HOW to do something it is very easy to get lost
on WHAT needs to get done.

RAUL

Muks wrote:

no!
Not available in verilog-2k

Constrained random verification is introduced in System Verilog only.

$Muks

 

[Muks]

You are right but I am also not wrong...

It is possible to do constrained random verification using only Verilog
2001.
With "only verilog 2001" is not possible, you can use C alongwith, as

you mentioned.

But, System Verilog is complete solution.


Regards
$Muks

 

[Ajeetha]

Hi,
Verilog PLI/VPI was intended to provide any thing that C can do into
Verilog domain. In particular, the issue with Constraint random
generation is more about the "constraint solving" than about the
constraint specification alone. In your case, it is very likely that
you wrote a solver (or used some thing else? I would be interested to
know). What SV brings to the desktop is to relieve users off such
painful stuff and makes vendors' job more difficult

Also, with SV - constraints become part of one language - than
spreading it across languages/domains/scripts etc.

My 2 cents
Ajeetha
www.noveldv.com