Converting logic_vector -> natural

[magik]

Hi

I want to convert vect(3 downto 0) into natural digit

is there any standard conversion procedure/function in vhdl for that??

Paul

 

[David Bishop]

magik wrote:

Hi

I want to convert vect(3 downto 0) into natural digit

is there any standard conversion procedure/function in vhdl for that??

use ieee.numeric_std.all;

.....
variable natvar : natural;
variable vect : std_logic_vector (3 downto 0);
......

natvar := to_integer(unsigned(vect));

 

[magik]

thanx!!

I used conv_integer from std_logic_unsigned and the result is the same


Uzytkownik "David Bishop" <dbishop@vhdl.org> napisal w wiadomosci
news:HJxve.54606$g5.22335@twister.nyroc.rr.com...

magik wrote:

Hi

I want to convert vect(3 downto 0) into natural digit

is there any standard conversion procedure/function in vhdl for that??

use ieee.numeric_std.all;

....
variable natvar : natural;
variable vect : std_logic_vector (3 downto 0);
.....

natvar := to_integer(unsigned(vect));

 

[Ralf Hildebrandt]

magik wrote:

I used conv_integer from std_logic_unsigned and the result is the same

Don't do it. First this library is /not/ a standard library. Your code is not protable.
Second you always assume /unsigned/ numbers in the vector. It is much better to treat
std_(u)logic_vectors neighter as signed nor as unsigned number in general and to choose it
using the conversion unsigned() or signed() dependend on the context.

O.k. - for your conversion to natural, which cover non-negative integers there is no
problem, but a conversion to integer would never lead to negative numbers.

Ralf