Converting integer to std_logic_vector

[Rockerboy]

Hi,

I am new to VHDL. I want to convert an integer to std_logic_vector of
length 32. Is there any in-built function in VHDL for this?

I am doing the following includes:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Thanks,
Abhishek

 

[KJ]

"Rockerboy" <rkabhi@gmail.com> wrote in message
news:8ddd4fbb-46f8-4fe2-a067-85617e3dc0cf@e25g2000prg.googlegroups.com...

Moments after I posted, I found conv_std_logic_vector is the right
function

Actually you shouldn't use std_logic_arith. It's not an IEEE standard, it's

just something that an early VHDL supplier came up with...it has some
issues.

What you should use instead is ieee.numeric_std. In that package are
to_unsigned() and to_signed() functions that convert integers into the
appropriate representations. unsigned and signed can then be simply
converted to std_logic_vector.

Usage example:
use ieee.numeric_std.all;
.....
my_slv <= std_logic_vector(to_unsigned(my_integer, my_slv'length)); -- if
my_integer is actually 'natural'
my_slv <= std_logic_vector(to_signed(my_integer, my_slv'length)); -- if
my_integer could be negative

KJ

 

[Rockerboy]

Moments after I posted, I found conv_std_logic_vector is the right
function

On Dec 5, 9:05 pm, Rockerboy <rka...@gmail.com> wrote:

Hi,

I am new to VHDL. I want to convert an integer to std_logic_vector of
length 32. Is there any in-built function in VHDL for this?

I am doing the following includes:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Thanks,
Abhishek

 

[tigerx]

Hi Abhishek,

there is an inbuilt function in VHDL to convert interger to
logic_vector.

In declaration do like this.

signal temp_integer: integer;
signal temp: std_logic_vector(31 downto 0);

Here how you can convert

temp <= conv_std_logic_vector(temp_integer,32);


Enjoy!!!


On Dec 6, 9:05 am, Rockerboy <rka...@gmail.com> wrote:

Hi,

I am new to VHDL. I want to convert an integer to std_logic_vector of
length 32. Is there any in-built function in VHDL for this?

I am doing the following includes:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Thanks,
Abhishek

 

[Dave]

On Dec 7, 1:51 pm, tigerx <mp.techpa...@googlemail.com> wrote:

Hi Abhishek,

there is an inbuilt function in VHDL to convert interger to
logic_vector.

In declaration do like this.

signal temp_integer: integer;
signal temp: std_logic_vector(31 downto 0);

Here how you can convert

temp <= conv_std_logic_vector(temp_integer,32);

Enjoy!!!

On Dec 6, 9:05 am, Rockerboy <rka...@gmail.com> wrote:



Hi,

I am new to VHDL. I want to convert an integer to std_logic_vector of
length 32. Is there any in-built function in VHDL for this?

I am doing the following includes:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Thanks,
Abhishek- Hide quoted text -

- Show quoted text -

No, really, use to_unsigned from numeric_std, and cast to
std_logic_vector like KJ says. It is the IEEE standard library for
signed and unsigned types. Especially when you're learning the
language, you want to learn to do things the right way, and build good
coding habits.

Changing the world, one engineering student at a time...

 

[Andy]

On Dec 7, 12:51 pm, tigerx <mp.techpa...@googlemail.com> wrote:

Hi Abhishek,

there is an inbuilt function in VHDL to convert interger to
logic_vector.

In declaration do like this.

signal temp_integer: integer;
signal temp: std_logic_vector(31 downto 0);

Here how you can convert

temp <= conv_std_logic_vector(temp_integer,32);

Enjoy!!!

On Dec 6, 9:05 am, Rockerboy <rka...@gmail.com> wrote:

Hi,

I am new to VHDL. I want to convert an integer to std_logic_vector of
length 32. Is there any in-built function in VHDL for this?

I am doing the following includes:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Thanks,
Abhishek

The conv_std_logic() function is not "inbuilt" in vhdl. It is a
function in a package that, while residing in the IEEE library in most
tools, is not an official part of the language standard or any IEEE
standard package. It was put there, in violation of the IEEE standard,
by synopsys, and everyone else has followed suit, to maintain
compatibility with synopsys.

The IEEE standard way to use arithmetic with vectors is to cast them
to numeric_std.signed or numeric_std.unsigned, as appropriate for the
values you are trying to use. The IEEE standard numeric_std package
includes conversions to and from signed/unsigned and integer.

Andy