Converting High Rise Time clock to Low Rise time clock - Che

D

Drew

Guest
Hello Guys,

I am facing this chellenge for a long time now. I have TTL compatible
clock (20MHz) with rise/fall time around 40 ns. It goes to my CPLD,
which outputs 3 clks of 10MHz, 5MHz and 2MHz. And the CPLD (MAX3032)
will also give around 40 ns rise/fall time I guess. I need rise/fall
times of < 2ns for my application. I have tried different things
including trying to buffer the clock but still doesnt work. I am sure
many people have come across this problem. Anybody has a solution(s)!

Thanks,
Drew
 
Any modern FPGA or CPLD will give you a (lightly loaded) rise or fall time
below 2 ns. Just stay away from the museum stuff.
Peter Alfke
=================================
From: dhruvish@gmail.com (Drew)
Organization: http://groups.google.com
Newsgroups: comp.arch.fpga
Date: 22 Jul 2004 07:11:47 -0700
Subject: Converting High Rise Time clock to Low Rise time clock - Chellenge!
Click to expand...
 
Drew wrote:
Hello Guys,

I am facing this chellenge for a long time now. I have TTL compatible
clock (20MHz) with rise/fall time around 40 ns. It goes to my CPLD,
which outputs 3 clks of 10MHz, 5MHz and 2MHz. And the CPLD (MAX3032)
will also give around 40 ns rise/fall time I guess. I need rise/fall
times of < 2ns for my application. I have tried different things
including trying to buffer the clock but still doesnt work. I am sure
many people have come across this problem. Anybody has a solution(s)!
Click to expand...
What did you buffer the clock with? If you use any sort of TTL or CMOS
inverter, buffer or gate, it should sharpen up the rising and falling
edges. You could even run the clock through the CPLD if you have two
spare pins, one input (not clock) and one output. Just have output :=
input.

You may not get a 2 ns rise time depending on the type of device you use
for a buffer. A faster logic family normally has a faster rise time.
Check the data sheet. If you are going through any standard logic
device as a buffer and you still have 40 ns rise time, there is
something else wrong, like maybe the scope you are measuring it with?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:40FFF1EF.8728981A@yahoo.com...
You may not get a 2 ns rise time depending on the type of device you use
for a buffer. A faster logic family normally has a faster rise time.
Check the data sheet. If you are going through any standard logic
device as a buffer and you still have 40 ns rise time, there is
something else wrong, like maybe the scope you are measuring it with?
Click to expand...
Or the probes?
I've made myself a pair of otherwise-not-too-good probes I use for high
speed stuff:
one meter of RG178*; On the scope end it's terminated with 50 ohm in the
plug, on the measurement end there's 950 ohm in series. They have 1/20 gain
and low impedance, true, but they've proved to be far 'truer' than anything
else I've used when soldered to the target (100 ps risetime with no ill
behaviour), even Tektronix' tip-grounded probes.

Do NOT use a spiral-cut metal film resistor as series resistor. 4*240 ohm
1206 SMT's are good on pcb with groundplane, 2*475 ohm 'flying' is also
good.

/Kasper
*because it's 1.9 mm thick and PTFE so it doesn't melt even when resoldered
for the umphteenth time, and it's overall nice stuff.
 
This bloke's published some good stuff. Check out
http://www.emcesd.com/1ghzprob.htm

cheers, Syms.
 
Drew wrote:

I am facing this chellenge for a long time now. I have TTL compatible
clock (20MHz) with rise/fall time around 40 ns. It goes to my CPLD,
which outputs 3 clks of 10MHz, 5MHz and 2MHz. And the CPLD (MAX3032)
will also give around 40 ns rise/fall time I guess. I need rise/fall
times of < 2ns for my application. I have tried different things
including trying to buffer the clock but still doesnt work. I am sure
many people have come across this problem. Anybody has a solution(s)!
Click to expand...
20MHz is 50ns, so the clock better have rise and fall times
less than 25ns each.

Maybe your scale is off?

-- glen
 
"Kasper Pedersen" <ngfilter@kasperkp.dk> wrote in message
news:40ffff50$0$159$edfadb0f@dtext02.news.tele.dk...
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:40FFF1EF.8728981A@yahoo.com...
You may not get a 2 ns rise time depending on the type of device you use
for a buffer. A faster logic family normally has a faster rise time.
Check the data sheet. If you are going through any standard logic
device as a buffer and you still have 40 ns rise time, there is
something else wrong, like maybe the scope you are measuring it with?

Or the probes?
I've made myself a pair of otherwise-not-too-good probes I use for high
speed stuff:
one meter of RG178*; On the scope end it's terminated with 50 ohm in the
plug, on the measurement end there's 950 ohm in series. They have 1/20
gain
and low impedance, true, but they've proved to be far 'truer' than
anything
else I've used when soldered to the target (100 ps risetime with no ill
behaviour), even Tektronix' tip-grounded probes.
Click to expand...

This technique is described in "High Speed Digital Design, A Handbook of
Black Magic" by Howard Johnson. A good book to have for general high speed
digital work.


Nial

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
Cyclone Based 'Easy PCI' proto board
www.nialstewartdevelopments.co.uk
 
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