converting floating point to fixed point

[H aka N]

Hi,

I need to convert floating point inputs (32 bits) to fixed point (11
bits for integer and 10 bits for the fraction) representation in a
synthesizable way. I would be more than grateful if someone could show
me the way.

I need to do this without using any special tools or such. Just pure
VHDL.

Best

 

[jens]

The first step is to define your requirements. Some questions you may
want to ask yourself (or whoever assigned this to you):

1. What is the format of the floating point number?
2. What should happen when the floating point number exceeds the bounds
of the fixed point number?
3. Since a lot of resolution is bound to be lost, what is gained by
doing this conversion?

 

[Mike Treseler]

H aka N wrote:

I need to convert floating point inputs (32 bits) to fixed point

http://groups.google.com/groups?q=vhdl+floating+fixed+point+200x

-- Mike Treseler

 

[Isaac Bosompem]

H aka N wrote:

Hi,

I need to convert floating point inputs (32 bits) to fixed point (11
bits for integer and 10 bits for the fraction) representation in a
synthesizable way. I would be more than grateful if someone could show
me the way.

I need to do this without using any special tools or such. Just pure
VHDL.

Best

I answered this question to someone a while ago in comp.lang.verilog.
Search in there.

 

[H aka N]

Dear Isaac,

many thanks for your reply, but unfortunately I couldn't find your
answer in comp.lang.verilog though I found some might be useful
answers. But even so I would be really grateful if you could dig out
your answer for me..

Best

H aka N

Isaac Bosompem wrote:

H aka N wrote:
Hi,

I need to convert floating point inputs (32 bits) to fixed point (11
bits for integer and 10 bits for the fraction) representation in a
synthesizable way. I would be more than grateful if someone could show
me the way.

I need to do this without using any special tools or such. Just pure
VHDL.

Best

I answered this question to someone a while ago in comp.lang.verilog.
Search in there.

 

[H aka N]

Dear Mike,

thanks a million for the link, but I cannot say that I found anything
useful here. I had done a similar search before.

I cannot use the vhdl-200x floating point and fixed point packages as I
am using XST and it (at least version 6.3) complains about negative
indexes, and there isn't much that can be done about it.

Best regards.

H aka N

 

[H aka N]

Dear Jens,

thanks for your time and trouble taken for writing the message.

Here are my answers:

1. 11 bits for integer part and 10 bits for the fractional part.
2. It will be clipped.. (There is a step in the logic where the
exceeding floating numbers will be clipped to the bounds of the fixed
number, so nothing to be worried about here)
3. The resolution needed is well below the 10 bits reserved for the
fractional part. I just cannot help that my inputs need to be floating
point (32 bits)..

Best,

H aka N

 

[Isaac Bosompem]

H aka N wrote:

Dear Isaac,

many thanks for your reply, but unfortunately I couldn't find your
answer in comp.lang.verilog though I found some might be useful
answers. But even so I would be really grateful if you could dig out
your answer for me..

Best

H aka N

Isaac Bosompem wrote:
H aka N wrote:
Hi,

I need to convert floating point inputs (32 bits) to fixed point (11
bits for integer and 10 bits for the fraction) representation in a
synthesizable way. I would be more than grateful if someone could show
me the way.

I need to do this without using any special tools or such. Just pure
VHDL.

Best

I answered this question to someone a while ago in comp.lang.verilog.
Search in there.

Hi, sorry about that, I actually posted it in comp.arch.embedded, link
is here:
http://groups.google.ca/group/comp.arch.embedded/browse_frm/thread/d58103d2c3bcf631/5e74bf3c53b29f2a?q=Fixed+Point&rnum=2#5e74bf3c53b29f2a

If you have any questions after reading it post them here.

 

[jens]

If you're not concerned about range checking or resolution, it becomes
quite simple... just shift the floating point number's mantissa left or
right, based on the floating point number's exponent and where the
decimal point needs to end up.

You haven't mentioned the format of the floating point number, so the
sizes of the mantissa/exponent and whether it's signed or unsigned will
need to be taken into account.

Doing it yourself might be easier than trying to modify the IEEE
libraries to work with XST.

 

[Ben Jones]

"H aka N" <hakan.sakman@gmail.com> wrote in message
news:1141291009.163060.222560@j33g2000cwa.googlegroups.com...

Hi Isaac,

thanks for the link, I viewed your solution, which I found to be very
neat, and put it here as a reference for the other folks:

Basically, add the implied integer bit(mask off mantissa and or with
0x800000)
Zero extend the result to 32-bits (ideally larger since you will risk
losing some integer bits, If the values that you have given represent
the range of FP values expected than 32-bits will be sufficient ).
Shift left this value, and decrement the exponent with each shift, if
unbiased exponent is positive.
Shift right this value, and increment the exponent with each shift, if
unbiased exponent is negative.
Repeat until the exponent = 0 (Remember to remove bias)
Take bits 31 - 24 as your integer portion and the bits below that as
your integer.
Bits 23-0 will be your fractional portion.
Last you will need to test the sign value to determine if negation of
the whole portion should take place.

I had a similar solution in mind but didn't know what to do with
floating point numbers below 1.0, many thanks for the input. I will be
coding this in vhdl soon and post the results here..

The method given above will work for all normalized floating-point numbers,
and so will always give you the right result even if the inputs are < 1.0.
You may need to add some extra logic to do the right thing when faced with
exceptional values such as infinities and NaNs. See the standard for
details.

You didn't specify how frequently you need to do this conversion operation.
This repeated shifting of the mantissa and incrementing of exponent is a
much easier, faster and smaller circuit if you can stand to do a multi-cycle
implementation, where the shifting happens one bit at a time (a bit like a
multi-cycle multiplier). However, if you need a circuit that can accept a
new input on every cycle, then it would have to be fully parallel. In that
case, you will have to take care to pipeline it or it will run very
slowly...

Cheers,

-Ben-

 

[H aka N]

Hi Mike,

I guess I need to stick with XST, and try out their new version, which
I am just about to order, in the hope of them having corrected this..

Best

 

[Phil Tomson]

In article <1141203510.504827.200170@v46g2000cwv.googlegroups.com>,
H aka N <hakan.sakman@gmail.com> wrote:

Dear Mike,

thanks a million for the link, but I cannot say that I found anything
useful here. I had done a similar search before.

I cannot use the vhdl-200x floating point and fixed point packages as I
am using XST and it (at least version 6.3) complains about negative
indexes, and there isn't much that can be done about it.

anyone know if this is still a problem with ISE 8.1?

Phil

 

[H aka N]

Hi Isaac,

thanks for the link, I viewed your solution, which I found to be very
neat, and put it here as a reference for the other folks:

I will use single precision.

As you may or may not know the IEEE754 format is as follows:

SEEEEEEEEMMMMMMMMMMMMMMMMMMMMMMM

S = Sign bit (0 = +, 1 = -)
E = 8-bit biased exponent (Bias = 0x7F)
M = Fractional portion/ Significand

The IEEE754 has a single implied integer bit of 1 (which is excluded
from the mantissa).

Really conversion from FP to Fixed point will be shifting and maybe
negation as well (only whole part, when negating, DO NOT touch the
fractional portion of the fixed point value).

Basically, add the implied integer bit(mask off mantissa and or with
0x800000)
Zero extend the result to 32-bits (ideally larger since you will risk
losing some integer bits, If the values that you have given represent
the range of FP values expected than 32-bits will be sufficient ).

Shift left this value, and decrement the exponent with each shift, if
unbiased exponent is positive.

Shift right this value, and increment the exponent with each shift, if
unbiased exponent is negative.
Repeat until the exponent = 0 (Remember to remove bias)
Take bits 31 - 24 as your integer portion and the bits below that as
your integer.

Bits 23-0 will be your fractional portion.
Say if you are using 16.16 fixed point you will have to truncate the
fractional portion. So the Leat significant byte of the fractional
portion will have to be discarded.

Last you will need to test the sign value to determine if negation of
the whole portion should take place.

I had a similar solution in mind but didn't know what to do with
floating point numbers below 1.0, many thanks for the input. I will be
coding this in vhdl soon and post the results here..


All the best.

H aka N
Hakan Sakman

 

[H aka N]

No but I am hoping to find out when I get my teeth and nails on ISE8.1

Best

H aka N
Hakan Sakman

 

[H aka N]

Hi Jens,

the incoming floating point data is 32 bits with msb:sign 8bits
exponent and 23 bits mantissa (standard single precision).

And the good thing is that I am only interested in positive fp upto
4096 integer. negative guys will be made zero and above 4096 are
truncated to 4096. And I will be representing this with 12bits.10bits
fixed point format..

Can you please detail the solution you have in mind a bit more?

Best..

H aka N