Converting a Verilog testbench to VHDL

K

Kevin Brace

Guest
Hi,

I am currently porting a Verilog HDL testbench to VHDL, and is having a
problem with VHDL's unforgiving (From Verilog user's prospective)
strongly-typed nature of its language.
Consider the following task in Verilog.


task Configuration_Read;

input[4:0] Device_Number;
input[2:0] Function_Number;
input[7:0] Register_Number;

(snip)

end task


The above task can be called from the following code.


Configuration_Read (1, 0, 8'h00, (snip));


So, I am trying to port the above code to VHDL, and this is how
it looks like.


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;


procedure Configuration_Read (

Device_Number : in unsigned(4 downto 0);
Function_Number : in unsigned(2 downto 0);
Register_Number : in unsigned(7 downto 0);

(snip)

end Configuration_Read;


It will be nice if the above procedure can be called from the
following code.


Configuration_Read (1, 0, X"00", (snip));


But the VHDL simulator gives me errors if I use the above code,
so I end up changing it to.


Configuration_Read (B"00001", B"000", X"00", (snip));


However, converting "1, 0," to "B"00001", B"000"," requires
quite a bit of work because I am going to have to repeat it many many
times, is harder to read, and is also error prone.
The testbench code is already done in Verilog, and is well debugged, so
what I am trying to do is to convert the Verilog version to VHDL with as
little effort as possible.
Having to quote a decimal with 'D""' like with binary or hexadecimal is
acceptable to me, but it looks like numeric_std doesn't support it.
I guess this is what I am talking about.


Configuration_Read (D"1", D"0", X"00", (snip));


Should I use integer or natural (Unsigned version of integer if
I understand it correctly.) instead of unsigned for Configuration_Read's
arguments?
I guess this is how it is going to look like. (I don't personally like it.)


procedure Configuration_Read (

Device_Number : in natural;
Function_Number : in natural;
Register_Number : in natural;

(snip)

end Configuration_Read;


Or, should I abandon the use of numeric_std, and instead use
the older, non-standard std_logic_unsigned and std_logic_arith? (I
personally don't want to do that.)


procedure Configuration_Read (

Device_Number : in std_logic_vector(4 downto 0);
Function_Number : in std_logic_vector(2 downto 0);
Register_Number : in std_logic_vector(7 downto 0);

(snip)

end Configuration_Read;


I personally will prefer to use unsigned in numeric_std because
it is part of an IEEE standard VHDL arithmatic library, and can handle
bit level manipulation, but I am not happy that I cannot seem to feed a
decimal number directly.
Let me know if there is a better way to handle the problem I am
experiencing.


Kevin Brace


--
Brace Design Solutions
Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available
for as little as $100 for non-commercial, non-profit, personal use.
http://www.bracedesignsolutions.com

Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.
 
Kevin Brace wrote:

I am currently porting a Verilog HDL testbench to VHDL, ...

input[4:0] Device_Number;
input[2:0] Function_Number;
input[7:0] Register_Number;

(snip)

Configuration_Read (B"00001", B"000", X"00", (snip));
Click to expand...
Note that those B's are optional since that is the default.

However, converting "1, 0," to "B"00001", B"000"," requires
quite a bit of work because I am going to have to repeat it many many
times, is harder to read, and is also error prone.
Click to expand...
I would use and editor macro.

The testbench code is already done in Verilog, and is well debugged, so
what I am trying to do is to convert the Verilog version to VHDL with as
little effort as possible.
Click to expand...
It will be considerable effort however you do it.

Having to quote a decimal with 'D""' like with binary or hexadecimal is
acceptable to me, but it looks like numeric_std doesn't support it.

Configuration_Read (D"1", D"0", X"00", (snip));
Click to expand...
There is no "D" bit-string literal in vhdl.
Numeric_std has nothing to do with it.

Your choices are B (default) H (hex) or O(octal).

Should I use integer or natural (Unsigned version of integer if
I understand it correctly.) instead of unsigned for Configuration_Read's
arguments?
Click to expand...
Natural is the non-negative range of integer.
The conversion is
my_vec_v := to_unsigned(natural_value, natural_length);


I would recommend either numeric_std.unsigned if you
need vectors, or just natural ranges say:
Device_Number_c : natural range 0 to 15

if the input is a natural to begin with.

-- Mike Treseler
 
Kevin,
Procedures like this are called many times,
however, you only write the procedure once.
Make the call easy and use natural. Use of
a conversion in the procedure can make the
type as you need it.


procedure Configuration_Read (

iDevice_Number : in natural;
iFunction_Number : in natural;
iRegister_Number : in natural;
. . .
) is
variable Device_Number : in unsigned(4 downto 0);
variable Function_Number : in unsigned(2 downto 0);
variable Register_Number : in unsigned(7 downto 0);
begin
Device_Number := to_unsigned(iDevice_Number, Device_Number'length) ;
Function_Number := to_unsigned(iFunction_Number, Function_Number'length) ;
Register_Number := to_unsigned(iRegister_Number, Register_Number'length) ;

(snip)

end Configuration_Read;

Of course with VHDL's overloading you can write it both
ways and decide later which one you like best.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~



Hi,

I am currently porting a Verilog HDL testbench to VHDL, and is having a
problem with VHDL's unforgiving (From Verilog user's prospective)
strongly-typed nature of its language.
Consider the following task in Verilog.


task Configuration_Read;

input[4:0] Device_Number;
input[2:0] Function_Number;
input[7:0] Register_Number;

(snip)

end task


The above task can be called from the following code.


Configuration_Read (1, 0, 8'h00, (snip));


So, I am trying to port the above code to VHDL, and this is how
it looks like.


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;


procedure Configuration_Read (

Device_Number : in unsigned(4 downto 0);
Function_Number : in unsigned(2 downto 0);
Register_Number : in unsigned(7 downto 0);

(snip)

end Configuration_Read;


It will be nice if the above procedure can be called from the
following code.


Configuration_Read (1, 0, X"00", (snip));


But the VHDL simulator gives me errors if I use the above code,
so I end up changing it to.


Configuration_Read (B"00001", B"000", X"00", (snip));


However, converting "1, 0," to "B"00001", B"000"," requires
quite a bit of work because I am going to have to repeat it many many
times, is harder to read, and is also error prone.
The testbench code is already done in Verilog, and is well debugged, so
what I am trying to do is to convert the Verilog version to VHDL with as
little effort as possible.
Having to quote a decimal with 'D""' like with binary or hexadecimal is
acceptable to me, but it looks like numeric_std doesn't support it.
I guess this is what I am talking about.


Configuration_Read (D"1", D"0", X"00", (snip));


Should I use integer or natural (Unsigned version of integer if
I understand it correctly.) instead of unsigned for Configuration_Read's
arguments?
I guess this is how it is going to look like. (I don't personally like it.)


procedure Configuration_Read (

Device_Number : in natural;
Function_Number : in natural;
Register_Number : in natural;

(snip)

end Configuration_Read;


Or, should I abandon the use of numeric_std, and instead use the
older, non-standard std_logic_unsigned and std_logic_arith? (I
personally don't want to do that.)


procedure Configuration_Read (

Device_Number : in std_logic_vector(4 downto 0);
Function_Number : in std_logic_vector(2 downto 0);
Register_Number : in std_logic_vector(7 downto 0);

(snip)

end Configuration_Read;


I personally will prefer to use unsigned in numeric_std because
it is part of an IEEE standard VHDL arithmatic library, and can handle
bit level manipulation, but I am not happy that I cannot seem to feed a
decimal number directly.
Let me know if there is a better way to handle the problem I am
experiencing.


Kevin Brace
Click to expand...
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top